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CSR Bit Fields

RISC-V henvcfgh CSR Register

Address 0x61APrivilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

henvcfgh is a RV32 upper half of henvcfg.

Related Search Terms
henvcfgh CSRhenvcfgh 0x61Aupper 32 bits of henvcfgHypervisor
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32STCE31RWPBMTE30RWADUE29RWReserved28:0
Field Map

Understand henvcfgh By Bit Fields

3 key fields
31

STCE

RW

RV32 henvcfg[63]: Sstc enable bit for the VS-mode vstimecmp access path.

STCE (bit 31) — RV32 henvcfg[63]: Sstc enable bit for the VS-mode vstimecmp access path.

What This Field Controls

  • - RV32 henvcfg[63]: Sstc enable bit for the VS-mode vstimecmp access path.

Common Values

0Disabled

VS-mode access to stimecmp, actually vstimecmp, raises a virtual-instruction exception.

1Enabled

Allows VS-mode to access the Sstc-defined vstimecmp.

↗Open Official Manual
30

PBMTE

RW

RV32 henvcfg[62]: controls whether Svpbmt is available for VS-stage address translation.

PBMTE (bit 30) — RV32 henvcfg[62]: controls whether Svpbmt is available for VS-stage address translation.

What This Field Controls

  • - RV32 henvcfg[62]: controls whether Svpbmt is available for VS-stage address translation.

Common Values

0Disabled

VS-stage address translation behaves as though Svpbmt were not implemented.

1Enabled

Svpbmt is available for VS-stage address translation.

↗Open Official Manual
29

ADUE

RW

RV32 henvcfg[61]: controls hardware updating of VS-stage PTE A/D bits.

ADUE (bit 29) — RV32 henvcfg[61]: controls hardware updating of VS-stage PTE A/D bits.

What This Field Controls

  • - RV32 henvcfg[61]: controls hardware updating of VS-stage PTE A/D bits.

Common Values

0Disabled

VS-stage address translation behaves as though Svade were implemented, requiring software handling of A/D bits.

1Enabled

Hardware updating of PTE A/D bits is enabled for VS-stage address translation.

↗Open Official Manual
Official Basis & Search Notes

henvcfgh is a RV32 upper half of henvcfg. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

henvcfgh address, access class, and width are checked against the official CSR tables: 0x61A, HRW, 32-bit RV32 high half.
henvcfgh fields are interpreted by the corresponding Hypervisor extension section; unimplemented fields must not be treated as fixed writable bits.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - henvcfgh is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing henvcfgh, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can henvcfgh be accessed through a supervisor CSR alias?

Do not treat henvcfgh as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.