CSR Bit Fields
RISC-V henvcfgh CSR Register
Address 0x61APrivilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs
henvcfgh is the RV32 32-bit read/write alias for henvcfg[63:32]; it does not exist on RV64.
Related Search Terms
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand henvcfgh By Bit Fields
0 key fields
Official Basis & Search Notes
henvcfgh is the RV32 32-bit read/write alias for henvcfg[63:32]; it does not exist on RV64.
It carries henvcfg's upper-half STCE, PBMTE, ADUE, DTE, PMM, and WPRI bits; every optional field is constrained by its defining extension and conditions.
What To Check First When Reading This CSR
- - This separate high-half CSR exists only when the defining extension is implemented and XLEN=32; it does not exist on RV64.
- - The Privileged Architecture CSR table defines its address and HRW class; field writability and read-only-zero conditions depend on the defining extension and implementation.
Risk Checks Before Writing
- - Write only fields that are explicitly implemented and writable; do not assign portable software meaning to reserved or specification-required read-only-zero bits.
Put It Back Into A Real Flow
1
Confirm that H and the optional extension defining the field are implemented, then access it from an M or HS context.
2
On RV32, use this address for bits 63:32 of the corresponding 64-bit CSR; do not access this address on RV64.