R-type
R-type: Register-Register
Two source registers and one destination register. opcode gives the major class, while funct3 and funct7 further select the operation.
funct7
31..25rs2
24..20rs1
19..15funct3
14..12rd
11..7opcode
6..0310
Instruction Formats
RISC-V Instruction Format Online Reference: R/I/S/B/U/J Encoding Layout
This is the RISC-V instruction format online reference page, showing 32-bit instruction layouts for R/I/S/U base formats and B/J immediate variants, including opcode, rd, rs1, rs2, funct3, funct7, and immediate field layouts. Use it to quickly identify an instruction's format, understand how machine code fields are allocated, and how related instructions are encoded.
I-type
I-type: 12-bit Immediate / Load / JALR / SYSTEM
Contains a 12-bit immediate plus rs1/rd. Immediate arithmetic, loads, JALR, FENCE, CSR, and SYSTEM-class instructions use this layout or close variants.
imm[11:0]
31..20rs1
19..15funct3
14..12rd
11..7opcode
6..0310
S-type
S-type: Store
Write to memory. The immediate is split (high 7 bits at 31:25, low 5 bits at 11:7).
imm[11:5]
31..25rs2
24..20rs1
19..15funct3
14..12imm[4:0]
11..7opcode
6..0310
B-type
B-type: Conditional Branch
Conditional branch format. The branch offset is encoded in 2-byte units and immediate bits are distributed across several instruction-word positions.
imm[12|10:5]
31..25rs2
24..20rs1
19..15funct3
14..12imm[4:1|11]
11..7opcode
6..0310
U-type
U-type: Upper 20-bit Immediate
A 20-bit immediate occupies the upper part of the instruction word. LUI and AUIPC use this format.
imm[31:12]
31..12rd
11..7opcode
6..0310
J-type
J-type: JAL Jump
The jump format used by JAL. The jump offset is encoded in 2-byte units and immediate bits are rearranged by the specification.
imm[20|10:1|11|19:12]
31..12rd
11..7opcode
6..0310
Examples:jal
Special Encodings
CSR Instructions
CSR instructions are I-type variants under the SYSTEM major opcode. The csr field occupies bits[31:20], and funct3 distinguishes read/write, set, and clear forms.
System
ECALL/EBREAK and related SYSTEM instructions use I-type-style encoding space, but their semantics are defined by the SYSTEM class rather than ordinary immediate arithmetic.
C Extension (16-bit)
The C extension provides 16-bit compressed encodings to improve code density; compressed instructions are separate from the R/I/S/U base formats and B/J immediate variants shown here.
Next Learning Step
Understand how B/J/S/U immediates are assembled
The formats page shows field positions; the immediate encoding guide explains sign extension, branch/jal offset alignment, and how each immediate bit maps into the machine word.
Open Immediate Encoding GuideOfficial References
This page is organized with reference to the official RISC-V documents below for architecture, ABI, CSR, and pseudo-instruction notes; platform or OS ABI differences still need to be checked against their own specifications.
RISC-V Unprivileged ISA Manual
Base integer ISA, RV32/RV64, instruction formats, load/store, control flow, and atomic instruction semantics.
RISC-V Privileged Architecture Manual
Privilege modes, trap entry/return, CSRs, address translation, PMP, and interrupt-related architectural state.
RISC-V Assembly Programmer's Manual
Assembly syntax, pseudo-instructions, common expansions, register names, and programmer-visible conventions.
RISC-V ELF psABI Specification
Procedure calling convention, register preservation, stack alignment, ELF, DWARF, and relocation rules.