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EBREAK

RISC-V EBREAK Instruction Details

Instruction ManualI-type

Transfer control back to the debugging environment; generates a breakpoint exception

Instruction Syntax

ebreak
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
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Related Search Terms
EBREAK instructionRISC-V EBREAKebreak syntaxebreak encodingebreak I-typeebreak breakpoint

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

EBREAK uses opcode 1110011 (0x73), funct3 000, funct12 000000000001. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 1110011 (0x73)
funct3: 000 (0x0)
funct12: 000000000001 (0x001)

Instruction Behavior

EBREAK (I-type encoding with imm=1, rs1=x0, funct3=000, rd=x0, opcode=SYSTEM=1110011) generates a breakpoint exception, returning control to the debugger. Primary uses: debugger breakpoints, marking unreachable code paths (GCC __builtin_unreachable), and semihosting (service calls via EBREAK sequence). Previously named SBREAK.

Common Usage Scenarios

Debug & Monitoring

Understand this scenario with real code like «ebreak # transfer control to debugger».

Stack & Frame

Understand this scenario with real code like «ebreak # transfer control to debugger».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Differs from ECALL only at imm[0] (EBREAK=1, ECALL=0)
Semihosting requires special 3-instruction sequence (slli+ebreak+srai) to distinguish from debug breakpoints