RISC-V Instruction Decoder
Enter a 32-bit RISC-V machine word and inspect the corresponding assembly instruction, opcode, funct fields, register fields, and immediate layout. The current tool covers a verified integer-instruction subset.
Input
Accepts 0x-prefixed hex, 8 hex digits, 0b-prefixed binary, 32 binary bits, and unsigned decimal.
The current decoder only covers a verified subset of 32-bit R/I/S/B/U/J integer instructions, including selected CSR and RV64 instructions; compressed, A/F/D/C/V, and most privileged or FENCE instructions are reported as unsupported.
Decode Result
Built-in Accuracy Checks
These fixed examples cover R/I/S/B/U/J formats and act as regression checks for the decoder's core paths.
This page is organized with reference to the official RISC-V documents below for architecture, ABI, CSR, and pseudo-instruction notes; platform or OS ABI differences still need to be checked against their own specifications.
Base integer ISA, RV32/RV64, instruction formats, load/store, control flow, and atomic instruction semantics.
Privilege modes, trap entry/return, CSRs, address translation, PMP, and interrupt-related architectural state.
Assembly syntax, pseudo-instructions, common expansions, register names, and programmer-visible conventions.
Procedure calling convention, register preservation, stack alignment, ELF, DWARF, and relocation rules.