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A complete index of all pages, making it easy to find what you need.
Core Reference
- Instruction LibraryBrowse the complete RISC-V instruction set by extension, format, and category
- Register BrowserGeneral registers, ABI names, and CSRs at a glance
- ABI Calling ConventionParameter passing, register usage, and stack frame rules
- CSR WorkbenchControl and status registers with addresses, permissions, and bit fields
Tools
- Instruction EncoderEnter assembly and inspect the 32-bit machine word, opcode, and field breakdown
- Instruction DecoderDecode a 32-bit machine word into assembly, format, and field layout, then continue into the real instruction pages
- Immediate EncodingVisual guide to I/S/B/U/J immediate fields, sign extension, and branch/jal offset assembly
- Pseudo InstructionsSee how pseudo instructions expand into real assembly and jump to the related real instructions
- Instruction FormatsField layouts for R/I/S/U base formats and B/J immediate variants, linked with the encoder and decoder
- RV32 / RV64 CompareRegister width, load/store behavior, and pointer differences
Learning Resources
- Privilege ArchitectureInteractive guide to U/S/M modes, traps, CSR updates, delegation, and sret/mret return
- ECALL TrapU-mode ECALL, cause 8, medeleg[8], trap CSRs, and SRET/MRET return
- Page FaultUses load page fault cause 13 as the example; instruction and store/AMO page faults use different causes
- Timer InterruptCause 5, mideleg[5], and return context after a supervisor timer interrupt is pending
- Address TranslationSv32/Sv39/Sv48/Sv57 address split, page-table walk, superpage alignment, page faults, and PA composition
- GlossaryConcise explanations of core RISC-V architecture and privilege terms
- FAQCommon misconceptions for RISC-V architecture and kernel development beginners