load page fault cause 13

RISC-V Page Fault Example Demo

load instruction -> Sv39 walk/permission check -> cause 13 + xtval -> handler repair/reject -> retry or terminate

Step 1 / 4

FlowPC is the load instruction address; VA is the data virtual address accessed by that load.scause / stval

Load

→

Trap entry

→

Handler

→

xRET

Page fault trap layered flow

Layered by U/S/M privilege level to show the page fault control path; nodes focus on trap routing, the handler, and retry.

repairmedeleg[13]scause/stval · sret

Current step1/4

Load instruction and access addressPC 0x0000000000011048 / VA 0x0000004000a130

U-mode instruction

User mode executes one load; its virtual address enters translation and permission checks. satp provides the page-table context; the access type is load. A page fault is the result of failed translation or protection checks, not a standalone instruction.

This page tracks only a load page fault example.

U-mode

1U-mode

Load PC and access VA

PC/VAPC is the trapping load instruction address written to EPC; VA is the failed data virtual address that an informative tval may report.

User mode executes ld a0, 0(a1) at PC 0x0000000000011048; that load accesses VA 0x0000004000a130, which then enters translation and permission checks.

Retry load

PC=0x0000000000011048

S-mode

The hart writes the faulting load instruction address to sepc and writes 13 to scause for this load page fault; this example shows an informative stval carrying the failed virtual address, then redirects PC to stvec.BASE.

2Trap entry

S-mode trap entry

BASEThe current entry is stvec.BASE. medeleg[13] selects the S-mode target; delegation changes the target privilege level and CSR names, not cause=13.

Hardware writes sepc=load PC and scause=13; this example shows an informative stval=fault VA, then jumps to stvec.BASE.

3Handler

Repair mapping

PTEThe repair path highlights the difference from ECALL: the handler commonly does not advance EPC to the next instruction; it lets the original memory instruction retry.

The handler reads cause, EPC, and available tval information, then repairs the PTE. EPC still points at the load.

4Trap return

Trap return resumes U-mode

retryEPC still holds the faulting load PC; after return, execution does not skip the faulting load but repeats the same memory access.

SRET sets PC to the original load PC saved in EPC (0x0000000000011048) and restores return privilege state.

M-mode

How to read

SRET takes the original load PC from EPC; unlike the common ECALL EPC+4 path, a repaired page fault usually retries the same memory instruction.

Key notes

Boundaries that often get mixed up

virtual-memory

Page faults originate in address translation and PTE checks; the virtual-memory page shows VA splitting, PTEs, superpages, and PA composition.

EPC

After a successful repair, EPC commonly keeps the faulting load PC so the same memory access can retry.

medeleg[13]

medeleg[13] changes the trap target; it does not change the load page fault cause=13.

Official semantic boundary

Real page faults include instruction page fault (cause 12), load page fault (cause 13), and store/AMO page fault (cause 15); this page fixes only the load page fault cause 13 trap path. The concrete fault is determined by translation, PTE validity/reserved bits, permissions, U/SUM/MXR, A/D rules, superpage alignment, access type, and current privilege state.