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CSR Bit Fields

RISC-V satp CSR Register

Address 0x180Privilege SupervisorAccess RW / SXLENSupervisor address-translation and memory-protection CSRs

satp (0x180) is an SXLEN-bit supervisor read/write CSR holding the root page-table PPN and ASID and selecting the address-translation scheme with MODE.

Related Search Terms
satp CSRsatp 0x180satp MODE ASID PPNRISC-V page tablesupervisor address translationSv39 satp
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
MODE63:60WARLASID59:44WARLPPN43:0WARL
Field Map

Understand satp By Bit Fields

3 key fields
63:60

MODE

WARL

RV64 WARL address-translation mode. Implementations need not support every mode; a write with an unsupported MODE leaves every satp field unchanged.

MODE (bits 63:60) — RV64 WARL address-translation mode. Implementations need not support every mode; a write with an unsupported MODE leaves every satp field unchanged.

What This Field Controls

  • - RV64 WARL address-translation mode. Implementations need not support every mode; a write with an unsupported MODE leaves every satp field unchanged.

Common Values

0Bare

No paged address translation; when selecting Bare, the remaining fields must be written as zero.

1-7Reserved

Reserved encodings for RV64 satp.MODE; portable software must not write or depend on them.

8Sv39

Enables Sv39 paged virtual memory.

9Sv48

Enables Sv48 paged virtual memory.

10Sv57

Enables Sv57 paged virtual memory.

11Sv64 (reserved)

Reserved in this version for a future Sv64 scheme.

12-13Reserved

Reserved for future standard use.

14-15Custom use

Designated for custom use; no standard portable address-translation semantics are defined.

59:44

ASID

WARL

RV64 address-space identifier supporting per-address-space translation fences. ASIDLEN may be zero, is at most 16, and is implemented from the least-significant bit upward.

ASID (bits 59:44) — RV64 address-space identifier supporting per-address-space translation fences. ASIDLEN may be zero, is at most 16, and is implemented from the least-significant bit upward.

What This Field Controls

  • - RV64 address-space identifier supporting per-address-space translation fences. ASIDLEN may be zero, is at most 16, and is implemented from the least-significant bit upward.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

43:0

PPN

WARL

RV64 supervisor physical page number of the root page table, equal to its physical address divided by 4 KiB; this WARL field might not represent every physical page number.

PPN (bits 43:0) — RV64 supervisor physical page number of the root page table, equal to its physical address divided by 4 KiB; this WARL field might not represent every physical page number.

What This Field Controls

  • - RV64 supervisor physical page number of the root page table, equal to its physical address divided by 4 KiB; this WARL field might not represent every physical page number.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

satp is an SXLEN-bit supervisor read/write CSR that combines WARL MODE, ASID, and root page-table PPN fields so an address space can be switched atomically.

The official CSR table and Supervisor ISA Section 12.1.11 specify address 0x180, SRW access, and SXLEN width.
Figures 31 and 32 mark MODE, ASID, and PPN as WARL; an unsupported MODE leaves the entire register unchanged.
Writing satp implies neither page-table update ordering nor address-translation cache invalidation; SFENCE.VMA may be needed after page-table changes or ASID reuse.
RISC-V Privileged Architecture Manual v20260120 - Supervisor ISA 12.1.11RISC-V Privileged Architecture Manual v20260120 - CSR tableRISC-V Privileged Architecture Manual v20260120 - mstatus.TVM

What To Check First When Reading This CSR

  • - satp is an SXLEN-bit SRW CSR at address 0x180; U-mode cannot access it directly.
  • - In S-mode, reading or writing satp raises an illegal-instruction exception when mstatus.TVM=1.
  • - ASIDLEN can be discovered by writing ones to every ASID bit and reading back; implemented bits start at the ASID's least-significant end.

Risk Checks Before Writing

  • - Selecting Bare requires writing zero to all remaining bits; Bare with nonzero remaining bits makes both those field values and address-translation/protection behavior UNSPECIFIED.
  • - Among Bare encodings with nonzero remaining bits, RV32 encodings with ASID[8:7]=3 are designated for custom use and the others are reserved for future standard use; all such RV64 encodings are reserved for future standard use.
  • - If MODE is unsupported, the entire satp write has no effect: MODE, ASID, and PPN all remain unchanged.
  • - Writing satp neither orders page-table updates nor invalidates address-translation caches; execute SFENCE.VMA where required after page-table changes or ASID reuse.

Put It Back Into A Real Flow

1

Determine the implemented MODE values and ASIDLEN, and prepare the root page-table PPN in 4 KiB page units.

2

Update MODE, ASID, and PPN together in one satp write; when selecting Bare, write zero to every remaining bit.

3

Depending on whether page tables changed or an ASID is reused, execute a matching SFENCE.VMA before or after the satp write as required.

FAQ

Can satp be accessed from any privilege level?

No. It is an SRW CSR, so U-mode cannot access it directly; in S-mode, reading or writing satp also raises an illegal-instruction exception when mstatus.TVM=1.

What is easiest to miss when writing satp?

A satp write does not automatically invalidate address-translation caches or order earlier page-table updates. Also, Bare requires all remaining bits to be zero, and an unsupported MODE makes the entire write ineffective.