RISC-V Instruction Set Online Reference

Instructions · Registers · CSRs · ABI

RVOPcode is a developer-focused RISC-V instruction set online reference. Search by mnemonic, extension, function, scenario, register name, CSR name, or topic to quickly find instruction syntax, encodings, examples, pseudo-instruction expansions, ABI rules, and CSR field details.

Try: addi·jalr·mstatus·ra·call·I-type·function call

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Core Entry Points

Instruction Library

Look up RISC-V instruction syntax, encoding, semantics, examples, and related instructions

Instruction Encoder

Encode RISC-V assembly into machine code with opcode, funct fields, and immediate breakdown, then continue into formats and the instruction reference

Instruction Decoder

Decode a 32-bit machine word into assembly, format, and field layout, then continue into instruction details and encoding rules

Register Quick Reference

Browse x0-x31 registers online with ABI names, save conventions, and usage

ABI / Calling Convention

Learn RISC-V function calls, argument passing, return values, stack frames, and register save rules

Pseudo Instructions

See how RISC-V pseudo instructions expand to real instructions such as call, ret, li, and mv, then jump into the real instruction pages

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Arithmetic Control Transfer Jump Memory Load Memory Store Branch Logical Address Computation System Privileged Immediates & Constants HINT Shift Compare Cache & Sync 32-bit Operational 32-bit Shift CSR Operation Division Multiplication Atomic Operation Atomic Microarch Hints Address Generation Bit Manipulation Integer Operation Crypto Single-Bit Operation Conditional Operations System & Privileged Cache & Synchronization Floating-Point Arithmetic Floating-Point Load Floating-Point Store Floating-Point Convert Floating-Point Compare Data Movement FP Precision Compressed Instruction Jump & Control Transfer Stack & Functions Security Mechanisms Vector Crypto AES Vector Bit Manipulation GCM/GHASH SHA-256 SM3 SM4 Vector Operations Vector Config Integer Arithmetic Bitwise Operations Fixed-Point Arithmetic Vector Permutation Permutation Vector Add Floating-Point Vector Type Convert Mask Operations Vector Multiply-Add Register Move Vector Reduction Vector Subtract Vector Load Memory Access Indexed Access Vector Integer Multiply-Accumulate Carry/Borrow Multiply-Add Min/Max Vector Data Movement Merge/Select Vector FP Vector Mask Operations Multiply Scalar-Vector Transfer Whole Register Vector Fixed-Point Narrowing/Clip Multiply-Subtract Shift/Narrowing Bitwise Divide/Remainder Gather Vector Memory Store Vector Configuration vset Instructions Sign-Extend Slide Mask Logic Crypto & Security Memory Management System & Privilege

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Instruction of the Day

Instruction Library

Jump and Link J-type

Jump to PC-relative offset, storing return address (PC+4) in rd

jal rd, offset

Format: J-type

Related: jalr auipc beq

Branch if Equal B-type

Branch to PC-relative offset if rs1 equals rs2

beq rs1, rs2, offset

Format: B-type

Related: bne blt bge bltu bgeu

Add Immediate I-type

Add sign-extended 12-bit immediate to rs1, place result in rd

addi rd, rs1, imm

Format: I-type

Related: add sub lui slti

Load Word I-type

Load a 32-bit word from memory into rd

lw rd, offset(rs1)

Format: I-type

Related: sw lb lh lbu lhu

Register Quick Reference

RV32 / RV64 Compare

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Register	ABI	Role	Saved by
x0	zero	Zero constant	N/A
x1	ra	Function return address	Caller
x2	sp	Stack pointer	Callee
x3	gp	Global pointer; unallocatable and not modified by normal procedures.	N/A
x4	tp	Thread pointer for accessing thread-local storage (TLS); ordinary procedures should not modify it.	N/A
x5	t0	Temporary / alternate link register	Caller
x10	a0	Argument / Return value	Caller
x11	a1	Argument / Return value	Caller