RISC-V Instruction Set Online Reference

Instructions · Registers · CSRs · ABI

RVOPcode is a developer-focused RISC-V instruction set online reference. Search by mnemonic, extension, function, scenario, register name, CSR name, or topic to quickly find instruction syntax, encodings, examples, pseudo-instruction expansions, ABI rules, and CSR field details.

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Core Entry Points

Instruction Library

Look up RISC-V instruction syntax, encoding, semantics, examples, and related instructions

Instruction Encoder

Encode RISC-V assembly into machine code with opcode, funct fields, and immediate breakdown, then continue into formats and the instruction reference

Instruction Decoder

Decode a 32-bit machine word into assembly, format, and field layout, then continue into instruction details and encoding rules

Register Quick Reference

Browse x0-x31 registers online with ABI names, save conventions, and usage

CSR Reference

Find control and status register addresses, access rules, privilege levels, and related architectural state

Pseudo Instructions

See how RISC-V pseudo instructions expand to real instructions such as call, ret, li, and mv, then jump into the real instruction pages

Browse By Multiple Dimensions

By Function

Arithmetic Control Transfer Jump Memory Load Memory Store Branch Logical Address Computation System Trap Immediates & Constants Assembler pseudo-instruction No operation Shift Compare Cache & Sync 32-bit word operations 32-bit Shift 32-bit Operation CSR Operation Division Multiplication Atomic Atomic Operation May-Be-Operations Address Generation Bit Manipulation Integer Operation Crypto Single-Bit Operation Conditional Operations System & Privileged Microarch Hints Cache & Synchronization Floating-Point Arithmetic Floating-Point Load Floating-Point Store Floating-Point Convert Floating-Point Compare Floating-Point Bit Move Floating-Point Classify Floating-Point Load Immediate Data Movement FP Precision Compressed Instruction Jump & Control Transfer Stack & Functions Security Mechanisms Vector Crypto AES Vector Bit Manipulation GCM/GHASH SHA-2 SM3 SM4 Vector Operations Vector Config Integer Arithmetic Vector Integer Bitwise Fixed-Point Arithmetic Vector Permutation Permutation Vector Add Floating-Point Vector Type Convert Mask Operations Vector Multiply-Add Vector Multiply Register Move Vector Reduction Vector Subtract Vector Memory Vector Load Fault-Only-First Load Indexed Vector Load Multiply-Accumulate Carry/Borrow Multiply-Add Min/Max Vector Data Movement Merge/Select Vector FP Vector Mask Operations Multiply Scalar-Vector Transfer Vector-Vector Transfer Vector-Scalar Transfer Whole Register Move Vector Fixed-Point Narrowing/Clip Multiply-Subtract Shift/Narrowing Divide/Remainder Gather Vector Store Vector Configuration vset Instructions Sign-Extend Slide Indexed Vector Store Mask Logic Crypto & Security Memory Management System & Privilege

By Format

AMO AMO-type B-type C C-type C2 (Zcmp CMPP)CA format CA-format CB-format CBO MISC-MEM fixed fields CI format CI-format CJ format CL-format CR format CS-format CSS-format I-type I-type (OP-IMM)I-type (OP-IMM-32)I-type (OP-IMM-32, RV64)J-type OP-32 (R-type)OP-FP OP-FP conversion fields OP-FP move fields OP-IMM (I-type)OP-V OP-V (OPFVF)OP-V (OPFVV)OP-V (OPIVV)OP-V / OPFVF OP-V / OPFVV OP-V / OPFVV VFUNARY1 OP-V / OPIVI OP-V / OPIVV OP-V / OPIVX OP-V OPIVV (funct6=010101, funct3=000)OP-V OPIVX (funct6=010101, funct3=100)OP-V OPMVV (funct6=010010, vs1=01001, funct3=010)OP-V VXUNARY0 (funct3=010)OP-V vector configuration (immediate AVL)OP-V vector configuration (register vtype)OP-V vector-configuration format OP-V vector-vector form OP-VE (32-bit)OP-VE OPMVV (funct6=101000, vm=1, vs1=10001, funct3=010)OP-VE OPMVV (funct6=101100, vm=1, funct3=010)OP-VE vector-scalar form OP-VE vector-vector form OPFVF OPFVV OPIVI OPIVI (OP-V)OPIVV OPIVV (OP-V)OPIVX OPIVX (OP-V)OPMVV OPMVV (OP-V)OPMVX OPMVX (OP-V)R-type R-type (OP with bs in bits 31:30)R-type HINT (ADD x0, x0, x2)R-type HINT (ADD x0, x0, x3)R-type HINT (ADD x0, x0, x4)R-type HINT (ADD x0, x0, x5)R4-type S-type SHA2 OP-IMM fixed-selector fields STORE-FP SYSTEM (MOP.R.28)SYSTEM (MOP.RR.7)SYSTEM (R-type encoding)SYSTEM (Zimop MOP.R)SYSTEM I-type fields SYSTEM R-type SYSTEM R-type fields U-type U-type (AUIPC HINT)V-type V-type (OP-V / OPFVF)V-type (OP-V / OPFVV VFUNARY0)V-type (OP-V / OPFVV)V-type (OP-V / OPIVI)V-type (OP-V / OPIVV)V-type (OP-V / OPIVX)V-type (OP-VE / OPMVV)Vector OP-V (OPIVI)Vector OP-V (OPIVV)Vector OP-V (OPIVX)Vector OP-VE (OPMVV)Vector Store Zimop MOP.R SYSTEM fields Zimop MOP.RR SYSTEM fields

By Scenario

Address & Pointer Basic Arithmetic Register Operations Immediates & Constants Branch & Jump Function Call & Return Data Loading Data Storing Comparison & Detection Unsigned Bounds Checking Register difference Negation Bit Operations & Masks Debug & Monitoring System & Privilege Execution Environment Call Byte data loads Sign extension Zero extension Halfword data loads Unsigned Halfword Load Align code segments Leave space for inline code modifications Set-bit masks Bit-field combination Byte data storage Halfword data storage Bit operations and shifts Signed comparison Bit Operations Type Conversion Logical Operations Memory Ordering Device & IO Concurrent Synchronization 32-bit addition in RV64 Sign extension of a 32-bit result RV64I or RV32 Zilsd doubleword loads Base plus offset addressing Unsigned Data Load Doubleword data storage RV32 Zilsd register-pair storage 32-bit logical left shift Atomic & Sync CSR Access Self-modifying Code JIT Compilation Dynamic Code Generation Multiplication & Division XLEN-bit integer multiplication Signed product high half Multi-word signed multiplication Unsigned product high half RV64 low-32-bit integer multiplication Integer remainder RV64 Operations 32-bit Atomic Operations Signed Comparisons Bounded Updates Unsigned Comparisons Unsigned Bounds Atomic Bit Toggling LR/SC conditional update Atomic read-modify-write Zcmop MOP Extension-defined Address generation from unsigned word indices Unsigned word zero-extension and left shift Address calculation clz leading-zero count clzw leading-zero count cpop population count cpopw population count ctz trailing-zero count Integer Comparison Integer Min/Max Zero-Byte Detection Crypto & Security Network & Byte Order Rotate right Bitwise equality masks Inverting an XOR result Zero-extend low 16 bits Bit Manipulation Resource Management Construct branchless conditional-select sequences Extension Compatibility Zimop default zero write Extension redefinition System & Privileged Zimop extension compatibility Concurrency & Multi-core Power Optimization Floating-point arithmetic Numerical computing Numerical Computing Integer to FP conversion Single-Precision to signed 32-bit integer conversion FP-to-unsigned-integer conversion Floating-Point Conditions Fused Floating Point Floating-Point Compare FP bit construction NaN payload preservation raw encoding debugging FP bit inspection Sign Operations Floating-Point Bit Manipulation Class Mask NaN Classification Signed-Zero Classification 64-bit Numeric Conversion RV64 floating-point and 64-bit integer conversion Double-precision numerical computing Floating-Point Format Conversion Integer-to-FP conversion FP format conversion Double-Precision to signed 32-bit integer conversion Double-Precision to unsigned 32-bit integer conversion Double-precision class detection NaN classification double bit construction RV64 raw encoding debug double bit inspection Floating-Point Classification Distinguish signed zeros and NaN classes Floating-point to integer conversion Floating-point widening Numeric integer-to-floating-point conversion Floating-point format conversion Quad-Precision to signed 32-bit integer conversion Floating Point Basic Floating-Point Memory Data Load/Store Integer-to-Floating-Point Conversion Floating-Point-to-Integer Conversion Half-Precision to signed 32-bit integer conversion Floating-Point Bit Move Debugging Bit Patterns JavaScript integer conversion Modulo 2^32 conversion Floating-Point Constants RV32 Double Data Movement Floating-Point Rounding Numeric Format Handling Floating-Point Memory Access Convert FP32 data to BF16 interchange format Widen BF16 data to FP32 Loops & Iteration 16-bit no-operation Conditional branch against zero Indirect Jump & Return Compressed word load Stack Access Shift Operations Memory Store Compressed & Code Size Doubleword data load Stack-relative doubleword load Upper constant generation Stack-frame register saves Signed integer scaling Logical Right Shift Integer Subtraction Bitwise XOR Sign-extend a 32-bit sum Short-range jump and link Arrays & Memory Access Halfword data load Compressed integer arithmetic Compressed integer bit operations Signed byte-value extension Signed halfword-value extension Compact halfword stores Zero Extension Function epilogue Function prologue Shadow-stack return-address checking Shadow-stack pop after a successful match Shadow-stack return-address copy storage Fixed-x1 compressed shadow-stack push Vector Acceleration Apply vector-scalar and-not to active vector elements.Apply whole-element bit reversal to active vector elements.Apply bit reversal within bytes to active vector elements.Apply carry-less multiply low to active vector elements.Apply vector-scalar carry-less multiply low to active vector elements.Per-element bit operation example Four SM4 rounds Vector round keys Widening logical shift Zero-extension bit operations Vector Integer Arithmetic Widening Operations Vectorized Loops Fixed-point averaging Vector data processing RVV masked execution Multi-word Integer Addition Per-element Carry Input Array Ops Add one integer scalar to active elements Keep or clear bits in each active element Fixed-point averaging subtraction with vxrm rounding Sparse Compression Stream Compaction Vector Integer Scaling Batch Quotients Scientific Computing DSP Vector Float Ops Numeric Classification NaN / Infinity Tests Vectorized Data Cleaning Integer data to FP vectors Mixed-type vector math Vectorized numeric preparation FP results to integer vectors Truncating numeric conversion frm-rounded conversion Vector normalization Scalar scaling Numeric computing Lane-wise FP division First Set Mask Bit Active Match Index Fused FP Accumulation Masked Element Multiply-Add Fused Multiplicand Overwrite Lane-wise FP maximum Lower-bound clipping Conditional Assignment Ternary Operator Lane-wise FP minimum Upper-bound clipping Fused multiply-subtract Scaling Gain Adjustment Vector FP Multiply Element-wise Multiply Reduction Result Scalar-Vector Interface Reduction Init Scalar to Element 0 Vector Init Constant Broadcast Compress after higher-precision FP computation Narrow FP vectors before storage Compress wide signed integers into narrower FP format Mixed integer/FP vector processing Compress wide unsigned integers into narrower FP format Vector numeric format conversion Multi-step FP narrowing Intermediate step to avoid double rounding Truncate wide FP to narrower signed integers Vectorized format conversion Format compaction needing truncation semantics Wide FP to narrower unsigned integers Store wide FP results as narrower signed integers Conversion before storage or integer post-processing Store wide FP results as narrower unsigned integers Vectorized format compaction Fused evaluation with both product and other term negated Negated-product fused operation Reciprocal scaling Division Optimization Newton-Raphson Vector Reduction Extremum Minimum Vector Sum Dot Product High-Perf Reduction Vector Normalization Constant Minus Vector Control vector signs from a scalar Vector copysign Lane-wise sign copy Lane-wise sign-bit copy Vector copysign construction Sign-bit teaching examples Control vector signs from an inverted scalar sign Bulk result sign selection Sign-bit inversion Lane-wise inverted sign injection Vector negative copysign construction Conditionally flip vector signs from a scalar Sign-bit XOR Keep or flip signs according to the scalar sign Lane-wise conditional sign flip Vector absolute-value / negation construction Lane-wise square root Vector norms Differences High-Precision Accum Mixed Precision Add a narrow FP vector to a wide FP vector Mixed-precision addition binary32 vectors promoted to binary64 mixed-precision FP compute entry higher-precision processing after widening integer vectors promoted to binary64 FP mixed-precision vector compute entry FP paths preserving 32-bit integer precision FP results to 64-bit integer vectors mixed-type vector conversion numeric paths needing double-width integer results SEW FP to 2*SEW integers active-element type conversion SEW multipliers with a 2*SEW addend active-element fused multiply-add Fused binary32 products with a binary64 old destination binary32 multipliers with binary64 products Widening Negated FMA Widening Ordered FP Sum Widening Unordered FP Sum High-Precision Difference Sequence Gen Loop Counter Gather Index Sparse Indexing Compress Helper Conditional Gather Contiguous Array Read Vectorized Memory Access Data-Dependent Exit Loops Contiguous Element Scanning Vector Loads That Can Trim vl Vectorized String Scan Contiguous Memory Probing Restore packed mask data Vector mask save/restore Mask spill/fill Ordered indirect reads Device or side-effecting address spaces Sparse table reads Structure field access Matrix row or column stride access Non-contiguous vector reads Sparse data reads Gather access without ordering needs Indirect array loads Gather using unsigned byte offsets Indexed reads without element-order guarantees Element-wise integer multiply-accumulate SEW-width multiply-add Multi-Precision Add BigInt Carry Propagation Elementwise integer multiply-add Elementwise maximum selection Data Clipping Thresholding Mask Widening Predicate mask generation FP condition testing NaN checks Vectorized conditional execution Generate FP comparison masks Select compared elements with v0.t Multi-Precision Sub Loop Termination Data-Dependent Exit Conditional Execution Range Check Predicate Generation Integer comparison Predicate mask Set-only-first mask General Multiply Fixed-Point Fractional Element 0 Setup Vector Constant Setup Copy vector-register body elements Vector initialization Integer scalar broadcast Read vector element 0 Extract a scalar vector result Compiler register shuffle Vector register group rearrangement Complete vector-register group copy Fixed-point result narrowing Vector DSP scaled output Wide-to-narrow conversion that needs a saturation flag Fixed-point scaled and rounded output Vector integer product subtraction Destructive SEW-width multiply-subtract Vector-scalar integer product subtraction Multiplicand-overwrite integer multiply-subtract SEW modular arithmetic Wide integer field extraction 2*SEW-to-SEW narrowing Wide-Source Field Extraction Integer Narrowing setting selected bits, combining bit fields, or merging per-element data bit patterns RVV per-element bit operations Loop Condition Mask Density Reduce a vector and seed by bitwise AND Reduce a vector and seed by signed maximum Reduce a vector and seed by unsigned maximum Reduce a vector and seed by signed minimum Single-width unsigned minimum reduction Seeded masked reduction Single-width bitwise OR reduction Single-width sum reduction Single-width bitwise XOR reduction Element-wise signed remainder Masked vector remainder Element-wise unsigned remainder Register table lookup Vector element permutation Elementwise reverse subtraction Vector negation Contiguous Array Write Stripmining Loop Vector Length Context Switch Vector State Restore Vector Integer Extension EEW-to-SEW extension V standard vector extension Register element rearrangement Rearrange elements by scalar offset Preserve low-index destination elements Vector Operations Power-of-2 Multiply Save packed mask data Mask-state save during context switching Signed fixed-point fractional multiplication Vector scaling with vxrm rounding Detecting saturation through vxsat Ordered indirect writes Sparse table updates Signed Shifts Bitfield Ops Non-contiguous vector writes Fixed-point scaling Vector shifts DSP data paths Element-wise vector differences Vector data subtraction Sparse data writes Scatter access without ordering needs Indirect array stores Widening Add Widening MAC Widening integer accumulation Widening integer multiplication Widening integer multiply Signed widening sum reduction Unsigned widening sum Vector reduction Statistical aggregation Signed Widening Subtraction Unsigned Widening Operations toggling selected bits, combining parity patterns, or building per-element difference masks Machine Learning Predicate condition composition Mask logical family comparison Mask construction before masked execution Polling an LR reservation set Waiting on shared state Reservation polling with a short timeout Cache & Hints Performance Write transfer for modified cache blocks Visibility to relevant non-coherent agents Data visibility between non-coherent agents Zero bytes corresponding to a cache block Data Protection Key Schedule SHA-256 σ0 transform SHA-256 σ1 transform SHA-256 Σ0 transform SHA-256 Σ1 transform SHA-512 σ0 transform SHA-512 hash transforms Integer-register bit operations Hash Algorithms Chinese National Crypto byte-local bit permutation per-byte bit reversal Forward-edge CFI Indirect call/jump marking Security hardening Packing low register halves Cryptographic bit manipulation Packing low register fields Shadow-stack switching Saving shadow-stack checkpoints Shadow-stack checkpoint maintenance Shadow-stack checking and unwinding Reading shadow-stack state Shadow-stack unwinding and switching Bit deinterleaving RV32 SHA3 bit-interleaved representation Register Lookup Register bit interleaving SHA3 bit interleaving M-mode handler return Firmware/SEE return OS kernel exception/interrupt return Idle loop power saving Low-power waiting TLB sync after page table mod Flush after munmap/mprotect Address space switch Debugger return Hardware breakpoint resume G-stage page-table sync VS-stage page-table sync Guest byte access Virtual-machine memory load VS/VU effective privilege Two-stage address translation Guest unsigned word reads Guest instruction-fetch emulation Guest memory writes Hypervisor Device Emulation Guest Memory Access Virtualized Instruction Simulation RNMI handler return Memory Management Translation Invalidation Translation Cache Invalidation Svinval Sequence G-stage invalidation sequence VS-stage invalidation sequence Code Optimization

Instruction of the Day

Instruction Library

Atomic Read/Write CSR I-type

Atomically read the old CSR value into rd and write rs1 to the same CSR; rd=x0 suppresses the CSR read

csrrw rd, csr, rs1

Format: I-type

Related: csrrs csrrc csrrwi

Add Upper Immediate to PC U-type

Add the 32-bit U-immediate offset to this instruction's PC; RV64 sign-extends the offset before writing rd

auipc rd, imm

Format: U-type

Related: lui jalr jal

Jump and Link J-type

Jump to PC-relative offset, storing return address (PC+4) in rd

jal rd, offset

Format: J-type

Related: jalr auipc beq

Branch if Equal B-type

Branch to PC-relative offset if rs1 equals rs2

beq rs1, rs2, offset

Format: B-type

Related: bne blt bge bltu bgeu

Register Quick Reference

RV32 / RV64 Compare

View All →

Register	ABI	Role	Saved by
x0	zero	Zero constant	Immutable
x1	ra	Function return address	Not preserved across calls
x2	sp	Stack pointer	Preserved across calls
x3	gp	Global pointer; unallocatable and not modified by standard ABI procedures.	Unallocatable
x4	tp	Thread pointer; unallocatable and not modified by standard ABI procedures.	Unallocatable
x5	t0	Temporary / alternate link register	Not preserved across calls
x10	a0	Argument / Return value	Not preserved across calls
x11	a1	Argument / Return value	Not preserved across calls