RISC-V Instruction Set Online Reference

Instructions · Registers · CSRs · ABI

RVOPcode is a developer-focused RISC-V instruction set online reference. Search by mnemonic, extension, function, scenario, register name, CSR name, or topic to quickly find instruction syntax, encodings, examples, pseudo-instruction expansions, ABI rules, and CSR field details.

Try: addi·jalr·mstatus·ra·call·I-type·function call

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Core Entry Points

Instruction Library

Look up RISC-V instruction syntax, encoding, semantics, examples, and related instructions

Instruction Encoder

Encode RISC-V assembly into machine code with opcode, funct fields, and immediate breakdown, then continue into formats and the instruction reference

Instruction Decoder

Decode a 32-bit machine word into assembly, format, and field layout, then continue into instruction details and encoding rules

Register Quick Reference

Browse x0-x31 registers online with ABI names, save conventions, and usage

CSR Reference

Find control and status register addresses, access rules, privilege levels, and related architectural state

Pseudo Instructions

See how RISC-V pseudo instructions expand to real instructions such as call, ret, li, and mv, then jump into the real instruction pages

Browse By Multiple Dimensions

By Function

Arithmetic Control Transfer Jump Memory Load Memory Store Branch Logical Address Computation System Trap Immediates & Constants HINT Shift Compare Cache & Sync 32-bit Operational 32-bit Shift CSR Operation Division Multiplication Atomic Atomic Operation May-Be-Operations Address Generation Bit Manipulation Integer Operation Crypto Single-Bit Operation Conditional Operations System & Privileged Microarch Hints Cache & Synchronization Floating-Point Arithmetic Floating-Point Load Floating-Point Store Floating-Point Convert Floating-Point Compare Floating-Point Bit Move Data Movement FP Precision Compressed Instruction Jump & Control Transfer Stack & Functions Security Mechanisms Vector Crypto AES Vector Bit Manipulation GCM/GHASH SHA-2 SM3 SM4 Vector Operations Vector Config Integer Arithmetic Vector Integer Bitwise Fixed-Point Arithmetic Vector Permutation Permutation Vector Add Floating-Point Vector Type Convert Mask Operations Vector Multiply-Add Vector Multiply Register Move Vector Reduction Vector Subtract Vector Memory Vector Load Fault-Only-First Load Indexed Vector Load Multiply-Accumulate Carry/Borrow Multiply-Add Min/Max Vector Data Movement Merge/Select Vector FP Vector Mask Operations Multiply Scalar-Vector Transfer Vector-Vector Transfer Vector-Scalar Transfer Whole Register Move Vector Fixed-Point Narrowing/Clip Multiply-Subtract Shift/Narrowing Divide/Remainder Gather Vector Store Vector Configuration vset Instructions Sign-Extend Slide Indexed Vector Store Mask Logic Crypto & Security Memory Management System & Privilege

By Format

AMO AMO-type B-type C C-type C2 (Zcmp CMPP)CA format CA-format CB-format CBO MISC-MEM fixed fields CI format CI-format CJ format CL-format CR format CS-format CSS-format I-type I-type (HINT)I-type (OP-IMM)I-type (OP-IMM-32)I-type (OP-IMM-32, RV64)J-type OP-32 (R-type)OP-FP OP-FP conversion fields OP-FP move fields OP-IMM (I-type)OP-V OP-V (OPFVF)OP-V (OPFVV)OP-V (OPIVV)OP-V / OPFVF OP-V / OPFVV OP-V / OPFVV VFUNARY1 OP-V / OPIVI OP-V / OPIVV OP-V / OPIVX OP-V OPIVV (funct6=010101, funct3=000)OP-V OPIVX (funct6=010101, funct3=100)OP-V OPMVV (funct6=010010, vs1=01001, funct3=010)OP-V VXUNARY0 (funct3=010)OP-V vector arithmetic format OP-V vector configuration (immediate AVL)OP-V vector configuration (register vtype)OP-V vector-configuration format OP-V vector-immediate form OP-V vector-scalar form OP-V vector-vector form OP-VE OPMVV (funct6=101000, vm=1, vs1=10001, funct3=010)OP-VE OPMVV (funct6=101100, vm=1, funct3=010)OPFVF OPFVV OPIVI OPIVI (OP-V)OPIVV OPIVV (OP-V)OPIVX OPIVX (OP-V)OPMVV OPMVV (OP-V)OPMVX R-type R-type (OP with bs in bits 31:30)R-type HINT (ADD x0, x0, x2)R-type HINT (ADD x0, x0, x3)R-type HINT (ADD x0, x0, x4)R-type HINT (ADD x0, x0, x5)R4-type S-type SYSTEM (MOP.R.28)SYSTEM (MOP.RR.7)SYSTEM (R-type encoding)SYSTEM R-type SYSTEM R-type fields U-type U-type (AUIPC HINT)V-type V-type (OP-V / OPFVF)V-type (OP-V / OPFVV VFUNARY0)V-type (OP-V / OPFVV)V-type (OP-V / OPIVI)V-type (OP-V / OPIVV)V-type (OP-V / OPIVX)V-type (OP-VE / OPMVV)Vector OP-V (OPIVI)Vector OP-V (OPIVV)Vector OP-V (OPIVX)Vector OP-VE (OPMVV)Zimop MOP.RR SYSTEM fields

By Scenario

Address & Pointer Basic Arithmetic Register Operations Immediates & Constants Branch & Jump Function Call & Return Data Loading Data Storing Stack & Frame Comparison & Detection Type Conversion Numerical Computing Bit Operations & Masks Debug & Monitoring System & Privilege Execution Environment Call Network & Byte Order Arrays & Memory Access Pipeline padding and code alignment Replace disabled instructions (nopout)Placeholder for performance profiling Bit-field Combination Multiplication & Division Bit Operations Logical Operations Memory Ordering Device & IO Concurrent Synchronization RV64-Specific Operations Unsigned Data Load Atomic & Sync CSR Access Self-modifying Code JIT Compilation Dynamic Code Generation XLEN-bit integer multiplication Signed product high half Multi-word signed multiplication Unsigned product high half RV64 low-32-bit integer multiplication RV64 Operations 32-bit Atomic Operations Signed Comparisons Bounded Updates Unsigned Comparisons Unsigned Bounds Zcmop MOP Extension-defined Shift & Rotate Integer Comparison Integer Min/Max Zero-Byte Detection Crypto & Security Bit Manipulation Resource Management System & Privileged Extension Compatibility Concurrency & Multi-core Power Optimization Floating-point arithmetic Numerical computing Floating-Point Conditions Fused Floating Point Floating-Point Compare FP bit construction NaN payload preservation raw encoding debugging FP bit inspection Sign Operations Floating-Point Bit Manipulation FP Type Inspection NaN Detection Special Value Handling Math Library Double-precision numerical computing Geometry Scientific Computing Floating-Point Format Conversion Floating Point Basic double bit construction RV64 raw encoding debug double bit inspection Floating-Point Memory Data Load/Store Integer-to-Floating-Point Conversion Floating-Point-to-Integer Conversion Floating-Point Bit Move Debugging Bit Patterns JavaScript Engines WebAssembly Modular Arithmetic Floating-Point Constants RV32 Double Data Movement Floating-Point Rounding Numeric Format Handling Floating-Point Memory Access Compressed & Code Size Deep learning inference BF16 model deployment Memory bandwidth reduction BF16 type promotion BF16↔FP32 interop Loops & Iteration Cache & Hints Indirect Jump & Return Stack Access Shift Operations Memory Store Stack-frame register saves Signed integer scaling Vector Operations Compressed integer arithmetic Compressed integer bit operations Signed byte-value extension Signed halfword-value extension Compact halfword stores Stack & Functions Security Mechanisms Vector Acceleration Vector Integer Arithmetic Widening Operations Vectorized Loops Fixed-point averaging Vector data processing RVV masked execution Multi-precision Arithmetic Big Integer Add Array Ops keeping selected bits, clearing bit fields, or combining per-element bit masks RVV per-element bit operations Sparse Compression Stream Compaction Vector Integer Scaling Batch Quotients DSP Vector Float Ops Numeric Classification NaN / Infinity Tests Vectorized Data Cleaning Integer data to FP vectors Mixed-type vector math Vectorized numeric preparation FP results to integer vectors Truncating numeric conversion frm-rounded conversion Vector normalization Scalar scaling Numeric computing Lane-wise FP division Conditional Loop Mask Traversal Matrix Ops Polynomial Eval Matrix Multiply Signal Processing Constant Offset Polynomial Evaluation Scalar threshold clipping Lane-wise FP maximum Vector numeric comparison Upper-threshold selection Conditional Assignment Ternary Operator Lane-wise FP minimum Lower-threshold selection Series Summation Alternating Sign Scaling Gain Adjustment Vector FP Multiply Element-wise Multiply Reduction Result Scalar-Vector Interface Reduction Init Scalar to Element 0 Vector Init Constant Broadcast Compress after higher-precision FP computation Narrow FP vectors before storage Compress wide signed integers into narrower FP format Mixed integer/FP vector processing Compress wide unsigned integers into narrower FP format Vector numeric format conversion Multi-step FP narrowing Intermediate step to avoid double rounding Truncate wide FP to narrower signed integers Vectorized format conversion Format compaction needing truncation semantics Wide FP to narrower unsigned integers Store wide FP results as narrower signed integers Conversion before storage or integer post-processing Store wide FP results as narrower unsigned integers Vectorized format compaction Alternating Add/Sub Reciprocal scaling Division Optimization Newton-Raphson Vector Reduction Extremum Minimum Vector Sum Dot Product High-Perf Reduction Vector Normalization Constant Minus Vector Control vector signs from a scalar Vector copysign Lane-wise sign copy Lane-wise sign-bit copy Vector copysign construction Sign-bit teaching examples Control vector signs from an inverted scalar sign Bulk result sign selection Sign-bit inversion Lane-wise inverted sign injection Vector negative copysign construction Conditionally flip vector signs from a scalar Sign-bit XOR Vector absolute-value / negation construction Lane-wise conditional sign flip Lane-wise square root Vector norms Differences High-Precision Accum Mixed Precision binary32 vectors promoted to binary64 mixed-precision FP compute entry higher-precision processing after widening integer vectors promoted to binary64 FP mixed-precision vector compute entry FP paths preserving 32-bit integer precision FP results to 64-bit integer vectors mixed-type vector conversion numeric paths needing double-width integer results High-Precision Matrix Mixed-Precision ML High-Precision Sum Widening Sum High-Precision Difference Sequence Gen Loop Counter Gather Index Sparse Indexing Compress Helper Conditional Gather Contiguous Array Read Vectorized Memory Access Vectorized String Scan Contiguous Memory Probing Vector Loads That Can Trim vl Restore packed mask data Vector mask save/restore Mask spill/fill Ordered indirect reads Device or side-effecting address spaces Sparse table reads Structure field access Matrix row or column stride access Non-contiguous vector reads Sparse data reads Gather access without ordering needs Indirect array loads Convolution Matrix/Tensor Multi-Precision Add BigInt Carry Propagation Scale-Accumulate Data Clipping Thresholding Mask Widening Predicate mask generation FP condition testing NaN checks Vectorized conditional execution Multi-Precision Sub Loop Termination Data-Dependent Exit Conditional Execution Range Check Predicate Generation General Multiply Fixed-Point Fractional Element 0 Setup Vector Constant Setup Copy vector-register body elements Vector initialization Integer scalar broadcast Read vector element 0 Extract a scalar vector result Compiler register shuffle Vector register group rearrangement Complete vector-register group copy Fixed-point result narrowing Vector DSP scaled output Wide-to-narrow conversion that needs a saturation flag Fixed-point scaled and rounded output Vector integer product subtraction Destructive SEW-width multiply-subtract Vector-scalar integer product subtraction Fixed-Point Scaling Precision Reduction setting selected bits, combining bit fields, or merging per-element data bit patterns Loop Condition Mask Density Global Aggregate Normalization Condition Vector Modulo Cyclic Indexing Table Lookup Reorder Compress/Decompress Large Table Lookup Sparse Data Symmetric Range Complement Contiguous Array Write Stripmining Loop Vector Length Context Switch Vector State Restore Vector Integer Extension EEW-to-SEW extension V standard vector extension Data Shift Shift Register Power-of-2 Multiply Save packed mask data Mask-state save during context switching Fixed-point DSP fractional multiply Audio and signal-processing kernels Vector fixed-point code that needs a saturation flag Ordered indirect writes Sparse table updates Signed Shifts Bitfield Ops Non-contiguous vector writes Fixed-point scaling Vector shifts DSP data paths Sparse data writes Scatter access without ordering needs Indirect array stores Integer Multiply Multi-Precision Accumulation Multi-Precision Arithmetic Vector sum Dot product Statistical aggregation Unsigned widening sum Vector reduction Signed Widening Subtraction Unsigned Widening Operations toggling selected bits, combining parity patterns, or building per-element difference masks Machine Learning Predicate condition composition Mask logical family comparison Mask construction before masked execution Performance Data Protection Key Schedule Hash Algorithms Chinese National Crypto byte-local bit permutation per-byte bit reversal Forward-edge CFI Indirect call/jump marking Security hardening Register Bit Interleave Register Lookup M-mode handler return Firmware/SEE return OS kernel exception/interrupt return Idle loop power saving Low-power waiting TLB sync after page table mod Flush after munmap/mprotect Address space switch Debugger return Hardware breakpoint resume Virtualization memory management G-stage page-table sync VMID-scoped fence VS-stage page-table sync ASID-scoped fence Hypervisor device emulation Guest memory access Virtual-machine load Hypervisor Device Emulation Guest Memory Access Virtualized Instruction Simulation OS Interface Memory Management Translation Invalidation Translation Cache Invalidation Svinval Sequence Svinval sequence G-stage invalidation Virtualization TLB shootdown VS-stage invalidation Code Optimization

Instruction of the Day

Instruction Library

Branch if Equal B-type

Branch to PC-relative offset if rs1 equals rs2

beq rs1, rs2, offset

Format: B-type

Related: bne blt bge bltu bgeu

Add Immediate I-type

Add sign-extended 12-bit immediate to rs1, place result in rd

addi rd, rs1, imm

Format: I-type

Related: add sub lui slti

Load Word I-type

Load a 32-bit word from memory into rd

lw rd, offset(rs1)

Format: I-type

Related: sw lb lh lbu lhu

Store Word S-type

Store the full 32-bit value of rs2 to memory

sw rs2, offset(rs1)

Format: S-type

Related: lw sb sh

Register Quick Reference

RV32 / RV64 Compare

View All →

Register	ABI	Role	Saved by
x0	zero	Zero constant	N/A
x1	ra	Function return address	Caller
x2	sp	Stack pointer	Callee
x3	gp	Global pointer; unallocatable and not modified by normal procedures.	N/A
x4	tp	Thread pointer for accessing thread-local storage (TLS); ordinary procedures should not modify it.	N/A
x5	t0	Temporary / alternate link register	Caller
x10	a0	Argument / Return value	Caller
x11	a1	Argument / Return value	Caller