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CSRRW

RISC-V CSRRW Instruction Details

Instruction ManualI-type

Atomically read the old CSR value into rd and write rs1 to the same CSR; rd=x0 suppresses the CSR read

Instruction Syntax

csrrw rd, csr, rs1
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicsrCSR OperationSystem
Related Search Terms
CSRRW instructionRISC-V CSRRWcsrrw syntaxcsrrw encodingZicsr CSRRWCSR read writeCSRRW rd x0

Instruction Behavior

CSRRW is the Zicsr atomic CSR read/write instruction: in one instruction it writes the old CSR value, zero-extended to XLEN, to rd and writes rs1 to the same CSR. If rd=x0, the instruction does not read the CSR and causes no CSR read side effects, but the write still occurs from rs1. The CSR address field is 12 bits.

CSRRW Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

rd
csr
rs1
csrrw
,
,
Execution Context

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.

31..20
19..15
14..12
11..7
6..0
011111000000
csr[11:0]
00110
rs1
001
funct3
00101
rd
1110011
opcode
Execution Data Path
instruction
0x7C0312F3
opcode
1110011 -> SYSTEM
funct3
001 -> CSRRW
operands
rd=t0(x5), csr=0x7C0, rs1=t1(x6)
CSR read
0x7C0 -> 0x0000000A
rs1 source
t1(x6) -> 0x00000003
CSR update
CSR = 0x00000003
rd update
t0(x5) = 0x0000000A
Current Step

Receive the 32-bit CSRRW SYSTEM encoding

CSRRW is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C0312F3
syntax : csrrw t0(x5), 0x7C0, t1(x6)
result : t0(x5) = 0x0000000A; CSR = 0x00000003
CSR Bit Result
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
old CSR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
write value
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
write
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRW sends the old CSR value to rd while writing rs1 into the CSR. rd=x0 is a write-only CSR operation: no CSR read or read side effects, but the CSR write still occurs.

The CSR address field is 12 bits in csr[11:0] of the I-type SYSTEM encoding.
When rd=x0, CSRRW/CSRRWI do not read the CSR and cause no read side effects.
The CSRRW source is rs1; rs1=x0 means write zero, not suppress the write.
CSRRW always writes the CSR; a concrete CSR's writable bits, readback value, and field side effects are defined by that CSR's specification.
RISC-V Unprivileged ISA Manual, Zicsr

Common Usage Scenarios

CSR Access

Understand this scenario with real code like «csrrw x5, 0x7c0, x6 # x5 = old CSR; CSR = x6».

System & Privilege

Understand this scenario with real code like «csrrw x5, 0x7c0, x6 # x5 = old CSR; CSR = x6».

Pre-Use Checklist

Syntax Check
  • Verify the immediate field is within the valid range.
  • Confirm source register rs1 points to the correct operand.
Semantic Check
  • Check if the immediate sign-extension matches expectations.
  • Ensure the result register rd has a clear purpose.

Pitfalls / Common Confusions

rd=x0 suppresses the CSR read and read side effects; it does not turn CSRRW into a no-write instruction.
rs1=x0 writes zero to the CSR; this differs from the read-only special case of CSRRS/CSRRC.
The CSR address field is 12 bits; a concrete CSR's writable bits, readback value, and field side effects are defined by that CSR's specification.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.