Does atomic here mean a memory atomic?
No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.
CSRRS
RISC-V CSRRS Instruction Details
Instruction ManualI-typeRead the old CSR value into rd and atomically set CSR bits selected by rs1; rs1=x0 suppresses the CSR write
Instruction Syntax
csrrs rd, csr, rs1
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicsrCSR OperationSystem
Instruction Behavior
CSRRS is the Zicsr atomic CSR read-and-set instruction: it reads the old CSR value, zero-extends it to XLEN for rd, then uses 1 bits in rs1 as a mask to set corresponding CSR bits. If rs1=x0, it does not write the CSR and causes no CSR write side effects; it still reads the CSR.
CSRRS Decode And Execute Animation
Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.
rd
csr
rs1
csrrs
,
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Execution Context
The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.
31..20
19..15
14..12
11..7
6..0
011111000000
csr[11:0]
00110
rs1
010
funct3
00101
rd
1110011
opcode
Execution Data Path
instruction
0x7C0322F3
opcode
1110011 -> SYSTEM
funct3
010 -> CSRRS
operands
rd=t0(x5), csr=0x7C0, rs1=t1(x6)
CSR read
0x7C0 -> 0x0000000A
rs1 source
t1(x6) -> 0x00000005
CSR update
CSR = 0x0000000F
rd update
t0(x5) = 0x0000000A
Current Step
Receive the 32-bit CSRRS SYSTEM encoding
CSRRS is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.
encoding: 0x7C0322F3
syntax : csrrs t0(x5), 0x7C0, t1(x6)
result : t0(x5) = 0x0000000A; CSR = 0x0000000F
CSR Bit Result
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1
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0
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0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
old CSR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
mask
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The bit view shows the CSR value computation at the selected XLEN.
This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.
Quick Understanding & Search Notes
CSRRS reads the old CSR value and uses 1 bits in rs1 as a set mask. rs1=x0 is a read-only CSR access: read the CSR, but do not write it.
For ordinary read/write bits, the new CSR value for CSRRS can be understood as old_csr OR rs1_mask; special CSR fields are still governed by the official read-back and field-side-effect rules.
rs1=x0 suppresses the CSR write and write side effects.
rd=x0 only discards old-value writeback; it does not suppress the CSRRS read.
When rs1 is not x0 but holds zero, CSRRS still writes the CSR: it does not action per-field side effects, but it does action any side effects caused by writing the entire CSR.
Common Usage Scenarios
CSR Access
Understand this scenario with real code like «csrrs x5, 0x7c0, x6 # x5 = old CSR; set bits selected by x6».
System & Privilege
Understand this scenario with real code like «csrrs x5, 0x7c0, x6 # x5 = old CSR; set bits selected by x6».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
rs1=x0 suppresses the write and write side effects, but the CSR read still occurs; this is the basis of the CSRR pseudoinstruction.
For ordinary read/write bits, CSRRS can be understood as a set-by-mask operation; however, Zicsr notes that if some CSR bits read back differently from their underlying value, the RMW writeback can affect bits where the mask is 0.
rd=x0 discards the old value, but for CSRRS it does not suppress the CSR read.
FAQ
Are rd=x0 and rs1/uimm=0 the same?
No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.