CSRRS

RISC-V CSRRS Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and atomically set CSR bits selected by rs1; rs1=x0 suppresses the CSR write

Instruction Syntax

csrrs rd, csr, rs1

Operand Breakdown

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=010.

rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; rs1=[19:15] selects an integer source register.

Read the old CSR value, zero-extend to XLEN for rd (x0 discards it), and use the source mask to set writable bits. rd=x0 still reads the CSR.

rs1=x0 suppresses the CSR write; zero in a non-x0 register still attempts a write. Overlapping rd/rs1 uses the initial source value.

The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

ZicsrCSR OperationSystem

Related Search Terms

CSRRS instruction RISC-V CSRRS csrrs syntax csrrs encoding Zicsr CSRRS CSR set bits CSRRS rs1 x0

Instruction Behavior

CSRRS is the Zicsr atomic CSR read-and-set instruction: it reads the old CSR value, zero-extends it to XLEN for rd, then uses 1 bits in rs1 as a mask to set corresponding writable CSR bits. If rs1=x0, it does not write the CSR and causes no CSR write side effects; it still reads the CSR.

CSRRS Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

rs1

csrrs

Execution ContextXLENold CSR valuers1 value

Assume an implemented, accessible CSR with ordinary writable example bits. A read-only CSR write attempt shows an exception without committing results.

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00110

rs1

010

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C0322F3

opcode

1110011 -> SYSTEM

funct3

010 -> CSRRS

operands

rd=t0(x5), csr=0x7C0, rs1=t1(x6)

CSR read

0x7C0 -> 0x0000000A

rs1 source

t1(x6) -> 0x00000005

CSR update

CSR = 0x0000000F

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRS SYSTEM encoding

CSRRS is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C0322F3

syntax : csrrs t0(x5), 0x7C0, t1(x6)

result : t0(x5) = 0x0000000A; CSR = 0x0000000F

CSR Bit Result

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRS reads the old CSR value and uses 1 bits in rs1 as a set mask. rs1=x0 is a read-only CSR access: read the CSR, but do not write it.

For ordinary read/write bits, the new CSR value for CSRRS can be understood as old_csr OR rs1_mask; special CSR fields are still governed by the official read-back and field-side-effect rules.

rs1=x0 suppresses the CSR write and write side effects.

rd=x0 only discards old-value writeback; it does not suppress the CSRRS read.

When rs1 is not x0 but holds zero, CSRRS still writes the CSR: it does not action per-field side effects, but it does action any side effects caused by writing the entire CSR.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Zicsr 2.0 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Version 20260120, CSR Address Mapping Conventions

Common Usage Scenarios

CSR Access

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrs x5,0x7c0,x6 → x5=0xa, CSR=0xf (x6=5)

System & Privilege

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrs x5,0x7c0,x6 → x5=0xa, CSR=0xf (x6=5)

Pre-Use Checklist

Syntax Check

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=010.
rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; rs1=[19:15] selects an integer source register.

Semantic Check

Read the old CSR value, zero-extend to XLEN for rd (x0 discards it), and use the source mask to set writable bits. rd=x0 still reads the CSR.
rs1=x0 suppresses the CSR write; zero in a non-x0 register still attempts a write. Overlapping rd/rs1 uses the initial source value.
The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

Pitfalls / Common Confusions

rs1=x0 suppresses the write and write side effects, but the CSR read still occurs; this is the basis of the CSRR pseudoinstruction.

For ordinary read/write bits, CSRRS can be understood as a set-by-mask operation; however, Zicsr notes that if some CSR bits read back differently from their underlying value, the RMW writeback can affect bits where the mask is 0.

rd=x0 discards the old value, but for CSRRS it does not suppress the CSR read.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.