Are CSR instructions memory atomics?
No. Atomic here means the CSR read-modify-write is one instruction, not an AMO to memory.
CSRRSI
RISC-V CSRRSI Instruction Details
Instruction ManualI-typeRead CSR into rd, then atomically set bits in the CSR where the 5-bit immediate has 1s
Instruction Syntax
csrrsi rd, csr, uimm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicsrCSR OperationSystem
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
CSRRSI uses opcode 1110011 (0x73), funct3 110. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 1110011 (0x73)
funct3: 110 (0x6)
Instruction Behavior
CSRRSI is the immediate variant of CSRRS: reads the current CSR value (zero-extended to XLEN bits) into rd, then uses the 5-bit unsigned immediate (uimm[4:0]) as a bit mask to set the corresponding bits to 1. If uimm=0, the instruction writes nothing to the CSR and causes no write side effects, enabling safe read-only access. Due to the 5-bit limit, only CSR bits 0–4 can be affected. Commonly used to configure privilege-mode fields in mstatus (e.g., MPP, MPIE) that reside in the lower bits. The assembler pseudo-instruction CSRSI(csr, uimm) is encoded as CSRRSI x0, csr, uimm (set bits, discard old value).
Quick Understanding & Search Notes
CSRRSI is a Zicsr atomic CSR read-modify-write instruction. CSR addresses are 12 bits, and whether read/write side effects occur depends on rd and on rs1 or uimm being x0/0.
CSRRW does not read the CSR when rd=x0; CSRRS/CSRRC do not write the CSR when rs1=x0.
Immediate forms use a zero-extended 5-bit uimm; uimm=0 suppresses writes for CSRRSI/CSRRCI.
Accessing absent CSRs, insufficient privilege, or illegally writing read-only CSRs raises illegal-instruction.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «csrrsi x5, mstatus, 1 # x5 = old mstatus; set bit 0 in mstatus».
System & Privilege
Understand this scenario with real code like «csrrsi x5, mstatus, 1 # x5 = old mstatus; set bit 0 in mstatus».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only CSR bits 0–4 can be affected; higher bits require CSRRS with a register
uimm=0 is a special 'read-only' case — it does NOT 'clear' any bits
Every execution triggers CSR read side effects
FAQ
What does rd=x0 change?
For CSRRW it suppresses the CSR read and read side effects; CSRRS/CSRRC still read the CSR.