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CSRRSI

RISC-V CSRRSI Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and set CSR bits selected by 5-bit uimm; uimm=0 suppresses the CSR write

Instruction Syntax

csrrsi rd, csr, uimm

Operand Breakdown

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=110.

rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; uimm=[19:15] is 0..31, zero-extended to XLEN.

Read the old CSR value, zero-extend to XLEN for rd (x0 discards it), and use the source mask to set writable bits. rd=x0 still reads the CSR.

uimm=0 suppresses the CSR write and write side effects; nonzero uimm directly selects only the low 5 bits.

The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

ZicsrCSR OperationSystem

Related Search Terms

CSRRSI instruction RISC-V CSRRSI csrrsi syntax csrrsi encoding Zicsr CSRRSI CSR uimm set CSRRSI uimm

Instruction Behavior

CSRRSI is the immediate form of CSRRS: it reads the old CSR value, zero-extends it to XLEN for rd, then uses the 5-bit unsigned uimm as a low-bit mask to set corresponding writable CSR bits. If uimm=0, it does not write the CSR and causes no CSR write side effects; it still reads the CSR.

CSRRSI Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

uimm

csrrsi

Execution ContextXLENold CSR value

Assume an implemented, accessible CSR with ordinary writable example bits. A read-only CSR write attempt shows an exception without committing results.

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00101

uimm[4:0]

110

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C02E2F3

opcode

1110011 -> SYSTEM

funct3

110 -> CSRRSI

operands

rd=t0(x5), csr=0x7C0, uimm=5

CSR read

0x7C0 -> 0x0000000A

uimm source

5 -> 0x00000005

CSR update

CSR = 0x0000000F

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRSI SYSTEM encoding

CSRRSI is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C02E2F3

syntax : csrrsi t0(x5), 0x7C0, 5

result : t0(x5) = 0x0000000A; CSR = 0x0000000F

CSR Bit Result

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRSI uses 1 bits in the 5-bit uimm as a set mask. With uimm=0 it reads the CSR but does not write it.

uimm[4:0] is a zero-extended 5-bit mask.

uimm=0 suppresses the CSR write and write side effects.

For ordinary read/write bits, CSRRSI bit operation is old_csr OR uimm_mask; special CSR fields remain subject to official read-back and side-effect rules.

The uimm=0 CSRRSI form reads without writing the CSR; a concrete CSR's writable bits, readback value, and field side effects are defined by that CSR's specification.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Zicsr 2.0 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Version 20260120, CSR Address Mapping Conventions

Common Usage Scenarios

CSR Access

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrsi x5,0x7c0,1 → x5=0xa, CSR=0xb

System & Privilege

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrsi x5,0x7c0,1 → x5=0xa, CSR=0xb

Pre-Use Checklist

Syntax Check

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=110.
rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; uimm=[19:15] is 0..31, zero-extended to XLEN.

Semantic Check

Read the old CSR value, zero-extend to XLEN for rd (x0 discards it), and use the source mask to set writable bits. rd=x0 still reads the CSR.
uimm=0 suppresses the CSR write and write side effects; nonzero uimm directly selects only the low 5 bits.
The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

Pitfalls / Common Confusions

uimm is only a low-5-bit mask and cannot directly affect higher CSR bits.

uimm=0 is the read-only special case and performs no CSR write; a nonzero uimm directly selects only a low-5-bit mask, while special CSR fields remain governed by official read-back and field-side-effect rules.

rd=x0 discards the old value, but does not suppress the CSRRSI CSR read.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.