XLEN
The integer register width of the current ISA. XLEN=32 for RV32 and XLEN=64 for RV64.
Glossary
Glossary
A beginner-oriented glossary of high-frequency terms in RISC-V architecture, privilege levels, and kernel development. Each entry aims to be concise and accurate, perfect for quick reference when reading instructions, ABI, CSRs, and kernel code.
ABI
Application Binary Interface. The calling convention is only one part; ABI also covers register roles, stack layout, object files, relocation, and other binary-level contracts.
caller-saved
Registers protected by the caller. Save them before a call if you still need their values afterwards.
callee-saved
Registers that a callee must restore before returning if it uses them.
Sign Extension
When widening a signed value, the new high bits are filled with the original sign bit.
Zero Extension
When widening an unsigned value, all new high bits are filled with zero.
Immediate
A constant encoded directly inside an instruction instead of being loaded from a register first.
Pseudo Instruction
An assembly alias provided for convenience. The assembler expands it into real instructions.
Privilege Levels
RISC-V has three privilege modes: M-mode (highest, machine-level, firmware/debug), S-mode (middle, supervisor-level, OS kernel), U-mode (lowest, user-level, applications). S-mode is optional; embedded systems may only have M+U.
CSR
Control and Status Register, living in a separate 12-bit address space (numbers 0–4095). Accessed via dedicated instructions (csrrw/csrrs/csrrc). Manages and monitors CPU configuration, status, interrupts, and memory protection.
ecall
Environment-call instruction. It raises an environment-call exception; the subsequent trap path depends on current privilege, delegation, and execution environment. The trap PC records the ecall itself, not the following instruction.
mret / sret
mret returns from an M-mode trap, sret from an S-mode trap. They restore the pre-trap PC (from mepc/sepc), privilege mode (from mstatus.MPP/SPP), and interrupt enable state (MPIE→MIE / SPIE→SIE), while also updating those status bits as specified.
mepc / sepc
Machine/Supervisor Exception PC. On trap entry it stores the instruction address that caused the trap: for synchronous exceptions this is usually the faulting instruction itself; for interrupts it is the interrupted control-flow location. mret/sret use it to restore PC.
mtvec / stvec
Machine/Supervisor Trap Vector Base register. Holds the entry address of the trap handler. Lowest 2 bits specify mode: 0 (direct, all traps to BASE), 1 (vectored — sync exceptions to BASE, interrupts to BASE+4×cause).
mcause / scause
Trap cause register. MSB 1=interrupt, 0=exception. Lower bits encode the specific cause: e.g. interrupt 7=MTI, exception 2=illegal instruction, 8=ecall from U-mode, 12=instruction page fault.
mstatus / sstatus
Machine/Supervisor Status Register. mstatus contains M-mode trap state such as MIE/MPIE/MPP; sstatus is the S-mode-visible status view and contains SIE/SPIE/SPP and related S-mode fields. Extension state fields such as FS depend on implementation and extension state.
mtval / stval
Trap value register, used by some exceptions to provide extra diagnostic information. Address or page-fault exceptions commonly report the faulting virtual address; illegal-instruction exceptions may include instruction bits if the implementation provides a nonzero value, but the value may also be zero.
CLINT
A local interrupt/timer block name used by common platform implementations, not a required base-ISA component. Many older platforms use it for MSIP, mtime, mtimecmp, and related machine-level software/timer interrupt registers.
PLIC
A common name for a platform-level interrupt controller that aggregates external device interrupts and routes them to harts. External interrupt controllers are platform/implementation concerns, not base integer ISA instruction semantics.
PMP
Physical Memory Protection. M-mode configures R/W/X permissions and address-matching modes per physical region via pmpcfg/pmpaddr registers. Restricts physical memory access for lower privilege levels — a foundational security mechanism for embedded and M-mode firmware.
PTE
A Page Table Entry. In Sv39, each is 64 bits containing: V (valid), R/W/X (read/write/execute), U (user-accessible), G (global), A (accessed), D (dirty) flags, plus PPN (Physical Page Number). A non-leaf PTE has V=1 and R=W=X=0, indicating a pointer to the next-level page table.
Sv39
A 39-bit virtual-address scheme (common on RV64). Virtual addresses are sign-extended from bit 38; the scheme uses three levels of 4 KiB page tables with 512 entries per level (9-bit indices), covering 512 GiB. satp holds the root PPN; VPN[2]/VPN[1]/VPN[0] index each level, and the 12-bit offset selects a byte within the 4 KiB page.
satp
Supervisor Address Translation and Protection register. MODE selects the translation scheme, ASID distinguishes address spaces, and PPN points to the root page table. After switching address spaces or updating page tables, software commonly uses sfence.vma at the architecturally appropriate point so address-translation changes are visible to later instruction fetches and memory accesses.
Official References
This page is organized with reference to the official RISC-V documents below for architecture, ABI, CSR, and pseudo-instruction notes; platform or OS ABI differences still need to be checked against their own specifications.
RISC-V Unprivileged ISA Manual
Base integer ISA, RV32/RV64, instruction formats, load/store, control flow, and atomic instruction semantics.
RISC-V Privileged Architecture Manual
Privilege modes, trap entry/return, CSRs, address translation, PMP, and interrupt-related architectural state.
RISC-V Assembly Programmer's Manual
Assembly syntax, pseudo-instructions, common expansions, register names, and programmer-visible conventions.
RISC-V ELF psABI Specification
Procedure calling convention, register preservation, stack alignment, ELF, DWARF, and relocation rules.