1
Current running mode
First identify whether the hart is executing in U, S, or M privilege mode. Delegation eligibility, the CSR bank written, and the return mode all depend on this context.
HomeRISC-V Privileged ISA
RISC-V privilege levels: how applications, kernels, and machine software hand off control
Ordinary programs cannot directly manage every hardware resource. The RISC-V privileged architecture uses privilege modes to separate software layers, and traps hand exceptions, interrupts, and environment calls to a handler determined by the privileged architecture, current privilege mode, and delegation configuration.
Official-source boundary
The animation only teaches general trap behavior confirmed by the RISC-V Privileged Architecture Manual; timer, interrupt-controller, SBI, and Linux paths are only marked as simplified boundaries in related demos.
Privilege hierarchy
RISC-V privilege architecture separates software into control layers
To learn RISC-V privilege architecture, start with two ideas: statically, software runs in different privilege modes; dynamically, exceptions, interrupts, and environment calls use traps to hand control to a handler selected by the current privilege mode and delegation configuration, then MRET or SRET returns.
Privilege decreases from top to bottom
M
M-mode
Machine-level software
Highest privilege mode; every hart must implement it. M-mode manages machine-level state and can access implemented lower-privilege CSRs unless access controls forbid it.
↓
S
S-mode
Operating-system kernel
Optional Supervisor mode; commonly used by OS kernels, virtual memory, and delegated traps. S-mode cannot directly execute M-mode-only instructions or access M-mode-only CSRs.
↓
U
U-mode
Applications
Lowest privilege mode; ordinary applications typically run here and request execution-environment services through traps such as ECALL. U-mode cannot directly perform higher-privilege operations.
This is the common U/S/M learning view; U-mode and S-mode presence depends on the implementation and extensions, and virtualization-related layers are not expanded here.
Scope: U / S / MHighest: M-modeHandoff: trap -> handler -> MRET/SRET
H-extension / Hypervisor: The RISC-V Hypervisor extension adds virtualization state and virtual privilege modes such as VS/VU. To keep this learning path focused on U/S/M and trap fundamentals, this page only marks that scope.
Control handoff
Trap Control Handoff
All demo animations share this backbone: identify the current privilege mode, recognize the trap cause, choose the target layer by delegation and privilege rules, record architectural state, enter the handler, and return.
2
Trap cause appears
A synchronous exception comes from the current instruction, such as ECALL, an illegal instruction, or a page fault; an asynchronous interrupt is taken when enable and priority conditions allow it. Both use the trap mechanism.
3
Choose target layer
Delegable traps occurring below M-mode can be routed to S-mode by medeleg/mideleg; non-delegated, non-delegable, or M-mode traps enter M-mode.
4
Record return clues
Hardware writes the target level's xepc and xcause, and xtval when applicable; it also updates xstatus fields for the previous privilege mode and interrupt enable used by xRET.
5
Handler runs and returns
The PC jumps to the Direct or Vectored entry from mtvec/stvec. After the handler runs, MRET/SRET resumes execution according to the current xepc and xstatus return state, which software may have adjusted.
Learning boundaries
Keep These Boundaries Separate
Trap mechanism is not OS policy
The RISC-V privileged architecture defines trap entry, architectural state recording, and xRET return; syscall ABI, handler code, and scheduling policy belong to the OS, firmware, or execution environment.
Trap entry is not a full context switch
Hardware records only the trap state specified by the architecture. Full register context and thread-state save/restore are usually software work.
Delegation does not change the trap cause
medeleg/mideleg can route eligible traps that occur below M-mode to S-mode. They do not change the trap's cause code or turn OS policy into hardware behavior.