RVOPcode
Privilege overview
ECALL cause 8

RISC-V ECALL Trap

U-mode ecall -> trap entry -> handler -> return

Step 1 / 5Target: S-mode
FlowUser-mode execution reaches ECALL; the edge to the target handler marks hardware Trap entry: cause 8, medeleg[8]=1, sepc/scause/stval=0 writes, sstatus-visible status-field updates, and stvec.BASE dispatch.sepc / sret
ECALL
→
Trap entry
→
Handler
→
EPC +4
→
xRET
Current step1/5

U-mode reaches ECALL

U-mode instruction

Execution is in U-mode at the ECALL instruction at address 0x4040. ECALL raises a synchronous exception; hardware then records the trapping address in the target EPC (sepc or mepc), records the cause in the target cause CSR (scause or mcause), saves return state, and enters the S-mode or M-mode path according to delegation configuration.

This page does not specify a concrete operating-system syscall ABI.

Key notes

Boundaries that often get mixed up

EPC

EPC first saves the ECALL instruction address, not the next instruction automatically.

ABI

Syscall numbers and argument locations are OS/execution-environment ABI policy, not fixed RISC-V ISA semantics.

medeleg[8]

medeleg[8] changes the trap target; it does not change ECALL cause=8.

Official semantic boundary

The official manual defines the ECALL trap and cause; the syscall ABI is OS/execution-environment policy.