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CSR Bit Fields

RISC-V medeleg CSR Register

Address 0x302Privilege MachineAccess RW / 64-bit; RV32 accesses the low/high halves through medeleg and medeleghMachine delegation, environment-configuration, and state-enable CSRs

Machine exception delegation register; on harts with S-mode, controls which synchronous exceptions can be delegated from S/U-mode to S-mode.

Related Search Terms
medeleg CSRmedeleg 0x302medeleg exception delegationmedeleg WARL bitsmedeleg medeleghRISC-V medeleg
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
ED63:0WARL
Field Map

Understand medeleg By Bit Fields

3 key fields
63:0

ED

WARL

Exception delegation bits. Bit N corresponds to exception code N; writable support is discovered by writing ones and reading back.

ED (bits 63:0) — Exception delegation bits. Bit N corresponds to exception code N; writable support is discovered by writing ones and reading back.

What This Field Controls

  • - Exception delegation bits. Bit N corresponds to exception code N; writable support is discovered by writing ones and reading back.

Common Values

0Not delegated

The corresponding trap is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Delegated to S-mode

The corresponding trap is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

11

Reserved/RO0

RO0

Read-only zero because machine-mode environment calls cannot occur in a less-privileged mode.

Reserved/RO0 (bit 11) — Read-only zero because machine-mode environment calls cannot occur in a less-privileged mode.

What This Field Controls

  • - Read-only zero because machine-mode environment calls cannot occur in a less-privileged mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

16

Double trap

RO0

Read-only zero; double trap is not delegatable.

Double trap (bit 16) — Read-only zero; double trap is not delegatable.

What This Field Controls

  • - Read-only zero; double trap is not delegatable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

medeleg controls whether synchronous exceptions from S/U-mode are taken directly by the S-mode trap handler. It is a 64-bit register; RV32 accesses the upper half through medelegh.

Implementations may support only a subset of delegatable exception bits; writing ones and reading back is the specified discovery method.
medeleg[11] and medeleg[16] read as zero by specification.
Exceptions that occur in M-mode are not delegated downward to S-mode by medeleg.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

  • - medeleg is required on harts with S-mode and should not exist on harts without S-mode.
  • - medeleg is architecturally a 64-bit read/write register; on RV32, medelegh aliases bits 63:32.
  • - Delegatable bits are implementation-subset WARL: write ones and read back to discover which exception causes can actually be delegated.

Risk Checks Before Writing

  • - Do not assume every exception-code bit is writable; unsupported or non-delegatable bits read back as zero.
  • - Delegation applies only to traps from S-mode or U-mode; traps never move from M-mode down to S-mode.

Put It Back Into A Real Flow

1

Write candidate delegation bits during privileged initialization.

2

Read back medeleg to discover the implemented delegation subset.

3

Configure S-mode trap state before enabling bits that delegate traps to S-mode.

FAQ

Can medeleg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records medeleg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing medeleg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.