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CSR Bit Fields

RISC-V medeleg CSR Register

Address 0x302Privilege MachineAccess RW / XLENMachine delegation, environment-configuration, and state-enable CSRs

Machine exception delegation register; controls which exceptions are delegated to S-mode.

Related Search Terms

medeleg CSR medeleg 0x302 exception delegation machine exception delegation medeleg bit fields RISC-V medeleg

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

ED63:0RW

Field Map

Understand medeleg By Bit Fields

14 key fields

XLEN-1:0

ED

Exception delegation bits; bit[N]=1 delegates exception N to S-mode

ED (bits XLEN-1:0) — Exception delegation bits; bit[N]=1 delegates exception N to S-mode.

What This Field Controls

- Exception delegation bits; bit[N]=1 delegates exception N to S-mode

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

IAM

Instruction address misaligned exception delegation bit.

IAM (bit 0) — Instruction address misaligned exception delegation bit.

What This Field Controls

- Instruction address misaligned exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

IAF

Instruction access fault exception delegation bit.

IAF (bit 1) — Instruction access fault exception delegation bit.

What This Field Controls

- Instruction access fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

ILL

Illegal instruction exception delegation bit.

ILL (bit 2) — Illegal instruction exception delegation bit.

What This Field Controls

- Illegal instruction exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

BP

Breakpoint exception delegation bit.

BP (bit 3) — Breakpoint exception delegation bit.

What This Field Controls

- Breakpoint exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

LAM

Load address misaligned exception delegation bit.

LAM (bit 4) — Load address misaligned exception delegation bit.

What This Field Controls

- Load address misaligned exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

LAF

Load access fault exception delegation bit.

LAF (bit 5) — Load access fault exception delegation bit.

What This Field Controls

- Load access fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

SAM

Store/AMO address misaligned exception delegation bit.

SAM (bit 6) — Store/AMO address misaligned exception delegation bit.

What This Field Controls

- Store/AMO address misaligned exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

SAF

Store/AMO access fault exception delegation bit.

SAF (bit 7) — Store/AMO access fault exception delegation bit.

What This Field Controls

- Store/AMO access fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

UECALL

Environment call from U-mode exception delegation bit.

UECALL (bit 8) — Environment call from U-mode exception delegation bit.

What This Field Controls

- Environment call from U-mode exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

SECALL

Environment call from S-mode exception delegation bit.

SECALL (bit 9) — Environment call from S-mode exception delegation bit.

What This Field Controls

- Environment call from S-mode exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

IPF

Instruction page fault exception delegation bit.

IPF (bit 12) — Instruction page fault exception delegation bit.

What This Field Controls

- Instruction page fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

LPF

Load page fault exception delegation bit.

LPF (bit 13) — Load page fault exception delegation bit.

What This Field Controls

- Load page fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

SPF

Store/AMO page fault exception delegation bit.

SPF (bit 15) — Store/AMO page fault exception delegation bit.

What This Field Controls

- Store/AMO page fault exception delegation bit.

Common Values

0Not delegated

The corresponding trap/exception is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding trap/exception is delegated to S-mode when it occurs below M-mode.

Official Basis & Search Notes

medeleg is a RW CSR in machine delegation, environment-configuration, and state-enable csrs at 0x302. Check privilege and implemented extensions before interpreting its bit fields.

medeleg address, lowest access privilege, and access class are checked against the official CSR table: 0x302, Machine, RW.

Read it as part of machine delegation, environment-configuration, and state-enable csrs before interpreting the bit-field table on this page.

Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements medeleg; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0x302 and the lowest access privilege (Machine) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads medeleg to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can medeleg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records medeleg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing medeleg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.