RISC-V medelegh CSR Register

Address 0x312Privilege MachineAccess RW / RV32 high-half / 32-bitMachine delegation, environment-configuration, and state-enable CSRs

medelegh at 0x312 is the RV32-only high-half CSR for medeleg, aliasing synchronous exception delegation bits medeleg[63:32].

Related Search Terms

medelegh CSR medelegh 0x312 RV32 medeleg high medeleg 63:32 exception delegation high RISC-V medelegh

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Field Map

Understand medelegh By Bit Fields

1 key fields

31:0 (aliases medeleg[63:32])

ED[63:32]

WARL

Upper 32 exception delegation bits of medeleg. The full 64-bit medeleg register is read/write; implementations may support only a subset of delegatable exceptions, discovered by writing ones and reading back.

ED[63:32] (bits 31:0 (aliases medeleg[63:32])) — Upper 32 exception delegation bits of medeleg. The full 64-bit medeleg register is read/write; implementations may support only a subset of delegatable exceptions, discovered by writing ones and reading back.

What This Field Controls

- Upper 32 exception delegation bits of medeleg. The full 64-bit medeleg register is read/write; implementations may support only a subset of delegatable exceptions, discovered by writing ones and reading back.

Common Values

0Disabled

The corresponding cause is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Enabled

The corresponding cause is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

Official Basis & Search Notes

medelegh is the RV32 access window for the upper half of the 64-bit medeleg register. It does not change delegation rules: only delegatable synchronous exceptions from S/U-mode are sent to S-mode, and M-mode traps are not delegated downward.

When XLEN=32, medelegh aliases medeleg[63:32]; it does not exist when XLEN=64.

Implementations may support only a subset of delegatable exception bits; write-one/read-back discovers them.

Traps delegated to S-mode write S-mode trap CSRs; nondelegated paths enter M-mode.

RISC-V Privileged Architecture Manual v20260120, CSR table RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

- medelegh exists only when XLEN=32; it does not exist when XLEN=64.
- medeleg/medelegh exist on harts with S-mode; harts without S-mode generally do not implement these CSRs.
- Delegatable exception bits are an implementation subset discovered by writing ones and reading back.

Risk Checks Before Writing

- Do not assume all high-half exception cause bits are delegatable; unsupported or nondelegatable bits read back as zero.
- Delegation applies only to traps from S/U-mode; M-mode traps are not delegated downward by medeleg/medelegh.

Put It Back Into A Real Flow

RV32 M-mode software reads medelegh to determine supported delegation bits in medeleg[63:32].

Set only exception-cause bits that should be delegated and read back as supported.

Validate delegation through S/U-mode trap paths; do not use M-mode traps to test downward delegation.

FAQ

Can medelegh be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records medelegh as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing medelegh?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.