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CSR Bit Fields

RISC-V mideleg CSR Register

Address 0x303Privilege MachineAccess RW / MXLENMachine delegation, environment-configuration, and state-enable CSRs

Machine interrupt delegation register; on harts with S-mode, M-mode controls which interrupts are delegated to S-mode handling.

Related Search Terms

mideleg CSR mideleg 0x303 mideleg interrupt delegation mideleg STIP SEIP mideleg WARL bits RISC-V mideleg

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

ID63:0WARL

Field Map

Understand mideleg By Bit Fields

4 key fields

MXLEN-1:0

ID

WARL

Interrupt delegation bits with the same layout as mip; supported writable bits are implementation-defined and discovered by write-one/read-back.

ID (bits MXLEN-1:0) — Interrupt delegation bits with the same layout as mip; supported writable bits are implementation-defined and discovered by write-one/read-back.

What This Field Controls

- Interrupt delegation bits with the same layout as mip; supported writable bits are implementation-defined and discovered by write-one/read-back.

Common Values

0Not delegated

The corresponding trap is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Delegated to S-mode

The corresponding trap is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

SSIP

WARL

Supervisor software interrupt delegation bit, when supported.

SSIP (bit 1) — Supervisor software interrupt delegation bit, when supported.

What This Field Controls

- Supervisor software interrupt delegation bit, when supported.

Common Values

0Not delegated

The corresponding trap is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Delegated to S-mode

The corresponding trap is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

STIP

WARL

Supervisor timer interrupt delegation bit, when supported. If delegated, STIs are not taken in M-mode.

STIP (bit 5) — Supervisor timer interrupt delegation bit, when supported. If delegated, STIs are not taken in M-mode.

What This Field Controls

- Supervisor timer interrupt delegation bit, when supported. If delegated, STIs are not taken in M-mode.

Common Values

0Not delegated

The corresponding trap is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Delegated to S-mode

The corresponding trap is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

SEIP

WARL

Supervisor external interrupt delegation bit, when supported.

SEIP (bit 9) — Supervisor external interrupt delegation bit, when supported.

What This Field Controls

- Supervisor external interrupt delegation bit, when supported.

Common Values

0Not delegated

The corresponding trap is not delegated to S-mode by this bit; if it occurs below M-mode and no other delegation path applies, it is taken by the M-mode trap handler.

1Delegated to S-mode

The corresponding trap is delegated to the S-mode trap handler when it occurs in S-mode or U-mode; traps from M-mode are not delegated downward.

Official Basis & Search Notes

mideleg controls which interrupts are delegated to S-mode. Its bit layout matches mip, with common bits including SSIP, STIP, and SEIP.

Implementations may support only a subset of delegatable interrupt bits; write-one/read-back discovers them.

A delegated interrupt is masked at M-mode and handled through the S-mode path.

mideleg bits for machine-level interrupts must not be fixed read-only one.

RISC-V Privileged Architecture Manual v20260120, CSR table RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

- mideleg is required on harts with S-mode and should not exist on harts without S-mode.
- mideleg is an MXLEN-bit read/write register with bit positions matching mip.
- Supported delegatable interrupt bits are discovered by writing ones and reading back.

Risk Checks Before Writing

- Do not assume every mip bit is writable in mideleg; implementation-supported bits may be a subset.
- Bits corresponding to machine-level interrupts must not be fixed read-only one; lower-level interrupt bits may be read-only one.
- Delegated interrupts are masked at M-mode; clear delegation if the interrupt must be handled by M-mode.

Put It Back Into A Real Flow

Write candidate interrupt delegation bits during machine-mode initialization.

Read back mideleg to discover which interrupt delegation bits are implemented.

Ensure S-mode interrupt-enable and trap-vector state is configured before delegating interrupts to S-mode.

FAQ

Can mideleg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mideleg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mideleg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.