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CSR Bit Fields

RISC-V mideleg CSR Register

Address 0x303Privilege MachineAccess RW / XLENMachine delegation, environment-configuration, and state-enable CSRs

Machine interrupt delegation register; controls which interrupts are delegated to S-mode.

Related Search Terms
mideleg CSRmideleg 0x303interrupt delegationmachine interrupt delegationmideleg bit fieldsRISC-V mideleg
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
ID63:0RW
Field Map

Understand mideleg By Bit Fields

4 key fields
XLEN-1:0

ID

RW

Interrupt delegation bits; bit[N]=1 delegates interrupt N to S-mode

ID (bits XLEN-1:0) — Interrupt delegation bits; bit[N]=1 delegates interrupt N to S-mode.

What This Field Controls

  • - Interrupt delegation bits; bit[N]=1 delegates interrupt N to S-mode

Common Values

0Not delegated

The corresponding interrupt is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding interrupt is delegated to S-mode when it occurs below M-mode.

1

SSIP

RW

Supervisor software interrupt delegation bit.

SSIP (bit 1) — Supervisor software interrupt delegation bit.

What This Field Controls

  • - Supervisor software interrupt delegation bit.

Common Values

0Not delegated

The corresponding interrupt is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding interrupt is delegated to S-mode when it occurs below M-mode.

5

STIP

RW

Supervisor timer interrupt delegation bit.

STIP (bit 5) — Supervisor timer interrupt delegation bit.

What This Field Controls

  • - Supervisor timer interrupt delegation bit.

Common Values

0Not delegated

The corresponding interrupt is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding interrupt is delegated to S-mode when it occurs below M-mode.

9

SEIP

RW

Supervisor external interrupt delegation bit.

SEIP (bit 9) — Supervisor external interrupt delegation bit.

What This Field Controls

  • - Supervisor external interrupt delegation bit.

Common Values

0Not delegated

The corresponding interrupt is handled in M-mode or remains on the current higher-privilege path.

1Delegated to S-mode

The corresponding interrupt is delegated to S-mode when it occurs below M-mode.

Official Basis & Search Notes

mideleg is a RW CSR in machine delegation, environment-configuration, and state-enable csrs at 0x303. Check privilege and implemented extensions before interpreting its bit fields.

mideleg address, lowest access privilege, and access class are checked against the official CSR table: 0x303, Machine, RW.
Read it as part of machine delegation, environment-configuration, and state-enable csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mideleg; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x303 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mideleg to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mideleg be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mideleg as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mideleg?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.