CSR Bit Fields

RISC-V mip CSR Register

Address 0x344Privilege MachineAccess RW / XLENMachine status, trap, and interrupt CSRs

Machine interrupt-pending register; indicates which interrupts are currently pending.

The mip (Machine Interrupt Pending) CSR at address 0x344 indicates which interrupt sources currently have pending requests. It mirrors the same bit layout as mie: SSIP (bit 1), MSIP (bit 3), STIP (bit 5), MTIP (bit 7), SEIP (bit 9), and MEIP (bit 11). Pending bits may be set by hardware or by interrupt-controller state; machine software interrupts are normally requested through memory-mapped msip state. Together with mie, mstatus.MIE, and delegation state, mip helps determine M-mode interrupt delivery.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:14Reserved0
Field Map

Understand mip By Bit Fields

7 key fields
1

SSIP

RW

Supervisor-mode Software Interrupt Pending

SSIP (bit 1) — Supervisor-mode Software Interrupt Pending.

What This Field Controls

  • - Supervisor-mode Software Interrupt Pending

Common Values

0Not pending

The interrupt represented by SSIP is not pending.

1Pending

The interrupt represented by SSIP is pending; delivery also depends on enables, global interrupt state, and delegation.

3

MSIP

RO

Machine-mode Software Interrupt Pending; normally reflects memory-mapped msip or platform interrupt-controller state and should not be treated as an ordinary writable mip bit.

MSIP (bit 3) — Machine-mode Software Interrupt Pending; normally reflects memory-mapped msip or platform interrupt-controller state and should not be treated as an ordinary writable mip bit.

What This Field Controls

  • - Machine-mode Software Interrupt Pending; normally reflects memory-mapped msip or platform interrupt-controller state and should not be treated as an ordinary writable mip bit.

Common Values

0Not pending

The interrupt represented by MSIP is not pending.

1Pending

The interrupt represented by MSIP is pending; delivery also depends on enables, global interrupt state, and delegation.

5

STIP

RW

Supervisor-mode Timer Interrupt Pending

STIP (bit 5) — Supervisor-mode Timer Interrupt Pending.

What This Field Controls

  • - Supervisor-mode Timer Interrupt Pending

Common Values

0Not pending

The interrupt represented by STIP is not pending.

1Pending

The interrupt represented by STIP is pending; delivery also depends on enables, global interrupt state, and delegation.

7

MTIP

RO

Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp)

MTIP (bit 7) — Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp).

What This Field Controls

  • - Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp)

Common Values

0Not pending

The interrupt represented by MTIP is not pending.

1Pending

The interrupt represented by MTIP is pending; delivery also depends on enables, global interrupt state, and delegation.

9

SEIP

RW

Supervisor-mode External Interrupt Pending

SEIP (bit 9) — Supervisor-mode External Interrupt Pending.

What This Field Controls

  • - Supervisor-mode External Interrupt Pending

Common Values

0Not pending

The interrupt represented by SEIP is not pending.

1Pending

The interrupt represented by SEIP is pending; delivery also depends on enables, global interrupt state, and delegation.

11

MEIP

RO

Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism)

MEIP (bit 11) — Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism).

What This Field Controls

  • - Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism)

Common Values

0Not pending

The interrupt represented by MEIP is not pending.

1Pending

The interrupt represented by MEIP is pending; delivery also depends on enables, global interrupt state, and delegation.

13

LCOFIP

RO

Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

LCOFIP (bit 13) — Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

What This Field Controls

  • - Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

Common Values

0Not pending

The interrupt represented by LCOFIP is not pending.

1Pending

The interrupt represented by LCOFIP is pending; delivery also depends on enables, global interrupt state, and delegation.

Official Basis & Search Notes

mip is a RW CSR in machine status, trap, and interrupt csrs at 0x344. Check privilege and implemented extensions before interpreting its bit fields.

mip address, lowest access privilege, and access class are checked against the official CSR table: 0x344, Machine, RW.
Read it as part of machine status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.

Assembly Operation Examples

Read/write mip using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, mip
Read all currently pending interrupt sources
csrr t0, mip; andi t0, t0, 0x80; bnez t0, handle_mtip
Check if MTIP(bit7) is pending and branch

Relationship With Other CSRs

mip indicates whether each interrupt source is pending, using the same bit positions as mie. MSIP is reflected in mip for machine software interrupt pending state; machine software interrupts are normally triggered by writing the memory-mapped msip register, not by writing mip.MSIP directly.

Key Bit Field Reference

SSIP(bit1) S-mode software pending | MSIP(bit3) M-mode software pending | STIP(bit5) S-mode timer pending | MTIP(bit7) M-mode timer pending | SEIP(bit9) S-mode external pending | MEIP(bit11) M-mode external pending

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mip; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x344 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mip to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mip be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mip as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mip?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.