Machine interrupt-pending register; indicates which interrupts are currently pending.
The mip (Machine Interrupt Pending) CSR at address 0x344 indicates which interrupt sources currently have pending requests. It mirrors the same bit layout as mie: SSIP (bit 1), MSIP (bit 3), STIP (bit 5), MTIP (bit 7), SEIP (bit 9), and MEIP (bit 11). Pending bits may be set by hardware or by interrupt-controller state; machine software interrupts are normally requested through memory-mapped msip state. Together with mie, mstatus.MIE, and delegation state, mip helps determine M-mode interrupt delivery.
Supervisor-mode Software Interrupt Pending
SSIP (bit 1) — Supervisor-mode Software Interrupt Pending.
The interrupt represented by SSIP is not pending.
The interrupt represented by SSIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Machine-mode Software Interrupt Pending; normally reflects memory-mapped msip or platform interrupt-controller state and should not be treated as an ordinary writable mip bit.
MSIP (bit 3) — Machine-mode Software Interrupt Pending; normally reflects memory-mapped msip or platform interrupt-controller state and should not be treated as an ordinary writable mip bit.
The interrupt represented by MSIP is not pending.
The interrupt represented by MSIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Supervisor-mode Timer Interrupt Pending
STIP (bit 5) — Supervisor-mode Timer Interrupt Pending.
The interrupt represented by STIP is not pending.
The interrupt represented by STIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp)
MTIP (bit 7) — Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp).
The interrupt represented by MTIP is not pending.
The interrupt represented by MTIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Supervisor-mode External Interrupt Pending
SEIP (bit 9) — Supervisor-mode External Interrupt Pending.
The interrupt represented by SEIP is not pending.
The interrupt represented by SEIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism)
MEIP (bit 11) — Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism).
The interrupt represented by MEIP is not pending.
The interrupt represented by MEIP is pending; delivery also depends on enables, global interrupt state, and delegation.
Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.
LCOFIP (bit 13) — Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.
The interrupt represented by LCOFIP is not pending.
The interrupt represented by LCOFIP is pending; delivery also depends on enables, global interrupt state, and delegation.
mip is a RW CSR in machine status, trap, and interrupt csrs at 0x344. Check privilege and implemented extensions before interpreting its bit fields.
Read/write mip using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8
mip indicates whether each interrupt source is pending, using the same bit positions as mie. MSIP is reflected in mip for machine software interrupt pending state; machine software interrupts are normally triggered by writing the memory-mapped msip register, not by writing mip.MSIP directly.
SSIP(bit1) S-mode software pending | MSIP(bit3) M-mode software pending | STIP(bit5) S-mode timer pending | MTIP(bit7) M-mode timer pending | SEIP(bit9) S-mode external pending | MEIP(bit11) M-mode external pending
During initialization or the relevant privileged flow, software reads mip to observe the current state.
Modify only the target fields while preserving all other bits.
Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mip as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.