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CSR Bit Fields

RISC-V mip CSR Register

Address 0x344Privilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine interrupt-pending register; indicates which interrupts are currently pending.

The mip (Machine Interrupt Pending) CSR at address 0x344 indicates which interrupt sources currently have pending requests. It mirrors the same bit layout as mie: SSIP (bit 1), MSIP (bit 3), STIP (bit 5), MTIP (bit 7), SEIP (bit 9), and MEIP (bit 11). Pending bits may be set by hardware or by interrupt-controller state; machine software interrupts are normally requested through memory-mapped msip state. Together with mie, mstatus.MIE, and delegation state, mip helps determine M-mode interrupt delivery.

Related Search Terms

mip CSR mip 0x344 machine interrupt pending mip MSIP MTIP MEIP mip H interrupt aliases mip LCOFIP

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

PLATFORM63:16Platform-defined; per-bit RW/RO00RO0

PLATFORM63:16Platform-defined; per-bit RW/RO 015:14RO0SSIP1RW 00RO0

Field Map

Understand mip By Bit Fields

16 key fields

MXLEN-1:16

PLATFORM

Platform-defined; per-bit RW/RO

Interrupt identities 16 and above are designated for platform use; each corresponding mip pending bit may be writable or read-only. A writable bit can be cleared by writing zero, while a read-only bit requires another clearing mechanism.

PLATFORM (bits MXLEN-1:16) — Interrupt identities 16 and above are designated for platform use; each corresponding mip pending bit may be writable or read-only. A writable bit can be cleared by writing zero, while a read-only bit requires another clearing mechanism.

What This Field Controls

- Interrupt identities 16 and above are designated for platform use; each corresponding mip pending bit may be writable or read-only. A writable bit can be cleared by writing zero, while a read-only bit requires another clearing mechanism.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

15:14

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bits 15:14) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

LCOFIP

RW or RO0

Local counter-overflow interrupt pending; if Sscofpmf is implemented, read-write in mip and reflects a local counter-overflow interrupt request resulting from any mhpmeventn.OF bit being set; read-only zero if Sscofpmf is not implemented.

LCOFIP (bit 13) — Local counter-overflow interrupt pending; if Sscofpmf is implemented, read-write in mip and reflects a local counter-overflow interrupt request resulting from any mhpmeventn.OF bit being set; read-only zero if Sscofpmf is not implemented.

What This Field Controls

- Local counter-overflow interrupt pending; if Sscofpmf is implemented, read-write in mip and reflects a local counter-overflow interrupt request resulting from any mhpmeventn.OF bit being set; read-only zero if Sscofpmf is not implemented.

Common Values

0Not pending

The interrupt represented by LCOFIP is not pending.

1Pending

The interrupt represented by LCOFIP is pending; delivery also depends on enables, global interrupt state, and delegation.

SGEIP / 0

hip alias with H; otherwise RO0

Supervisor guest external interrupt pending when H is implemented, aliasing hip.SGEIP; read-only zero without H.

SGEIP / 0 (bit 12) — Supervisor guest external interrupt pending when H is implemented, aliasing hip.SGEIP; read-only zero without H.

What This Field Controls

- Supervisor guest external interrupt pending when H is implemented, aliasing hip.SGEIP; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MEIP

Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism)

MEIP (bit 11) — Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism).

What This Field Controls

- Machine-mode External Interrupt Pending (read-only, set by platform-specific mechanism)

Common Values

0Not pending

The interrupt represented by MEIP is not pending.

1Pending

The interrupt represented by MEIP is pending; delivery also depends on enables, global interrupt state, and delegation.

VSEIP / 0

hip alias with H; otherwise RO0

Virtual supervisor external interrupt pending when H is implemented, aliasing hip.VSEIP; read-only zero without H.

VSEIP / 0 (bit 10) — Virtual supervisor external interrupt pending when H is implemented, aliasing hip.VSEIP; read-only zero without H.

What This Field Controls

- Virtual supervisor external interrupt pending when H is implemented, aliasing hip.VSEIP; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

SEIP

Supervisor external interrupt pending; if S-mode is implemented, writable in mip and read as the logical OR of the software-writable bit and the external interrupt-controller signal; CSR writes/read-modify-writes update only the software-writable bit. Read-only zero if S-mode is not implemented.

SEIP (bit 9) — Supervisor external interrupt pending; if S-mode is implemented, writable in mip and read as the logical OR of the software-writable bit and the external interrupt-controller signal; CSR writes/read-modify-writes update only the software-writable bit. Read-only zero if S-mode is not implemented.

What This Field Controls

- Supervisor external interrupt pending; if S-mode is implemented, writable in mip and read as the logical OR of the software-writable bit and the external interrupt-controller signal; CSR writes/read-modify-writes update only the software-writable bit. Read-only zero if S-mode is not implemented.

Common Values

0Not pending

The interrupt represented by SEIP is not pending.

1Pending

The interrupt represented by SEIP is pending; delivery also depends on enables, global interrupt state, and delegation.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 8) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MTIP

Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp)

MTIP (bit 7) — Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp).

What This Field Controls

- Machine-mode Timer Interrupt Pending (read-only, set by hardware when mtime >= mtimecmp)

Common Values

0Not pending

The interrupt represented by MTIP is not pending.

1Pending

The interrupt represented by MTIP is pending; delivery also depends on enables, global interrupt state, and delegation.

VSTIP / 0

hip alias with H; otherwise RO0

Virtual supervisor timer interrupt pending when H is implemented, aliasing hip.VSTIP; read-only zero without H.

VSTIP / 0 (bit 6) — Virtual supervisor timer interrupt pending when H is implemented, aliasing hip.VSTIP; read-only zero without H.

What This Field Controls

- Virtual supervisor timer interrupt pending when H is implemented, aliasing hip.VSTIP; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

STIP

RW or RO

Supervisor timer interrupt pending; writable in mip if stimecmp is not implemented; read-only and reflecting the supervisor timer interrupt signal from stimecmp if stimecmp is implemented; read-only zero if S-mode is not implemented.

STIP (bit 5) — Supervisor timer interrupt pending; writable in mip if stimecmp is not implemented; read-only and reflecting the supervisor timer interrupt signal from stimecmp if stimecmp is implemented; read-only zero if S-mode is not implemented.

What This Field Controls

- Supervisor timer interrupt pending; writable in mip if stimecmp is not implemented; read-only and reflecting the supervisor timer interrupt signal from stimecmp if stimecmp is implemented; read-only zero if S-mode is not implemented.

Common Values

0Not pending

The interrupt represented by STIP is not pending.

1Pending

The interrupt represented by STIP is pending; delivery also depends on enables, global interrupt state, and delegation.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 4) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MSIP

Machine software-interrupt pending, normally read-only and reflecting memory-mapped msip. If the system has only one hart, or the platform delivers machine-level interprocessor interrupts through machine external interrupts instead, mip.MSIP and mie.MSIE may both be read-only zero.

MSIP (bit 3) — Machine software-interrupt pending, normally read-only and reflecting memory-mapped msip. If the system has only one hart, or the platform delivers machine-level interprocessor interrupts through machine external interrupts instead, mip.MSIP and mie.MSIE may both be read-only zero.

What This Field Controls

- Machine software-interrupt pending, normally read-only and reflecting memory-mapped msip. If the system has only one hart, or the platform delivers machine-level interprocessor interrupts through machine external interrupts instead, mip.MSIP and mie.MSIE may both be read-only zero.

Common Values

0Not pending

The interrupt represented by MSIP is not pending.

1Pending

The interrupt represented by MSIP is pending; delivery also depends on enables, global interrupt state, and delegation.

VSSIP / 0

hip alias with H; otherwise RO0

Virtual supervisor software interrupt pending when H is implemented, aliasing hip.VSSIP; read-only zero without H.

VSSIP / 0 (bit 2) — Virtual supervisor software interrupt pending when H is implemented, aliasing hip.VSSIP; read-only zero without H.

What This Field Controls

- Virtual supervisor software interrupt pending when H is implemented, aliasing hip.VSSIP; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

SSIP

Supervisor software interrupt pending; if S-mode is implemented, writable in mip and may also be set to 1 by a platform-specific interrupt controller; read-only zero if S-mode is not implemented.

SSIP (bit 1) — Supervisor software interrupt pending; if S-mode is implemented, writable in mip and may also be set to 1 by a platform-specific interrupt controller; read-only zero if S-mode is not implemented.

What This Field Controls

- Supervisor software interrupt pending; if S-mode is implemented, writable in mip and may also be set to 1 by a platform-specific interrupt controller; read-only zero if S-mode is not implemented.

Common Values

0Not pending

The interrupt represented by SSIP is not pending.

1Pending

The interrupt represented by SSIP is pending; delivery also depends on enables, global interrupt state, and delegation.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 0) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mip is the MXLEN-bit Machine-mode interrupt-pending CSR at 0x344. Each bit reports whether the same-numbered interrupt is pending; trapping to M-mode also depends on mie, mstatus.MIE, and mideleg. Writability is defined per bit.

The official CSR table lists mip at 0x344 with Machine-mode read/write access.

Interrupt i traps to M-mode when mip[i] and mie[i] are both 1, the current privilege/global MIE condition is satisfied, and the interrupt is not delegated by mideleg.

MSIP, MTIP, and MEIP are read-only or conditionally read-only zero; SSIP, STIP, SEIP, and LCOFIP have conditional writability; H adds the SGEIP, VSEIP, VSTIP, and VSSIP aliases.

RISC-V Privileged Architecture Manual v20260120 RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

Assembly Operation Examples

Read/write mip using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, mip

Read all currently pending interrupt sources

csrr t0, mip; andi t0, t0, 0x80; bnez t0, handle_mtip

Check if MTIP(bit7) is pending and branch

Relationship With Other CSRs

mip indicates whether each interrupt source is pending, using the same bit positions as mie. MSIP is reflected in mip for machine software interrupt pending state; machine software interrupts are normally triggered by writing the memory-mapped msip register, not by writing mip.MSIP directly.

Key Bit Field Reference

What To Check First When Reading This CSR

- mip is the MXLEN-bit Machine-mode interrupt-pending CSR at 0x344.
- Each bit i corresponds to the same-numbered enable bit in mie; the standard low 16 bits cover standard interrupt causes, while bits 16 and above are designated for platform use.
- Writability is defined per pending bit: some bits are read-only and updated by a platform mechanism, timer mechanism, or memory-mapped control register.

Risk Checks Before Writing

- Write only pending bits that the official specification defines as writable; read-only bits must be cleared through the corresponding platform, timer, or memory-mapped mechanism.
- SEIP reads as the logical OR of the software-writable bit and the external interrupt-controller signal, but CSR writes and read-modify-writes update only the software-writable bit.
- After writes to mip, mie, mstatus, or mideleg, interrupt-trap conditions must be reevaluated in a bounded amount of time.

Put It Back Into A Real Flow

Read mip to see which interrupt sources are pending.

Use mie, mstatus.MIE, and mideleg to decide whether a pending interrupt will trap to M-mode.

Clear writable pending bits by writing 0; clear read-only pending bits through the corresponding platform or timer mechanism.

FAQ

Can mip be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR table gives the lowest access privilege; mip is at 0x344 with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mip?

When writing mip, distinguish writable and read-only pending bits per bit. A writable pending bit can be cleared by writing 0; a read-only pending bit must be cleared through the corresponding mechanism such as the platform interrupt controller, mtimecmp/stimecmp, or memory-mapped msip.