Supervisor interrupt-pending register; provides the view of mip interrupt-pending bits delegated to S-mode.
The sip (Supervisor Interrupt Pending) CSR at address 0x144 is the S-mode restricted view of mip, showing S-mode-relevant pending interrupts such as SSIP, STIP, and SEIP. For a pending interrupt to be serviced while running in S-mode, the corresponding enable bit in sie must be set and sstatus.SIE must permit interrupt delivery.
Fixed-zero bits in the standard interrupt region; read as zero.
Reserved (bit 0) — Fixed-zero bits in the standard interrupt region; read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Supervisor software-interrupt pending bit. If SSIP is delegated to S-mode, S-mode can read and write it through sip.
SSIP (bit 1) — Supervisor software-interrupt pending bit. If SSIP is delegated to S-mode, S-mode can read and write it through sip.
The interrupt represented by SSIP is not pending.
The interrupt represented by SSIP is pending; delivery also depends on sie and sstatus.SIE.
Fixed-zero bits in the standard interrupt region; read as zero.
Reserved (bit 2) — Fixed-zero bits in the standard interrupt region; read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Restricted view of the machine software-interrupt pending bit. It is visible in sip only when writable mideleg[3] is set; otherwise it reads zero. The underlying mip.MSIP bit is read-only.
MSIP (bit 3) — Restricted view of the machine software-interrupt pending bit. It is visible in sip only when writable mideleg[3] is set; otherwise it reads zero. The underlying mip.MSIP bit is read-only.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bit in the standard interrupt region; reads as zero.
Reserved (bit 4) — Reserved bit in the standard interrupt region; reads as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Supervisor timer-interrupt pending bit. If STIP is implemented and delegated to S-mode, it is read-only in sip; it is set/cleared by the execution environment, or reflects the stimecmp comparison when Sstc is implemented.
STIP (bit 5) — Supervisor timer-interrupt pending bit. If STIP is implemented and delegated to S-mode, it is read-only in sip; it is set/cleared by the execution environment, or reflects the stimecmp comparison when Sstc is implemented.
The interrupt represented by STIP is not pending.
The interrupt represented by STIP is pending; delivery also depends on sie and sstatus.SIE.
Fixed-zero bits in the standard interrupt region; read as zero.
Reserved (bit 6) — Fixed-zero bits in the standard interrupt region; read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Restricted view of the machine timer-interrupt pending bit. It is visible in sip only when writable mideleg[7] is set; otherwise it reads zero. The underlying mip.MTIP bit is read-only.
MTIP (bit 7) — Restricted view of the machine timer-interrupt pending bit. It is visible in sip only when writable mideleg[7] is set; otherwise it reads zero. The underlying mip.MTIP bit is read-only.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bit in the standard interrupt region; reads as zero.
Reserved (bit 8) — Reserved bit in the standard interrupt region; reads as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Supervisor external-interrupt pending bit. If SEIP is implemented and delegated to S-mode, it is read-only in sip; it is typically set and cleared by a platform interrupt controller.
SEIP (bit 9) — Supervisor external-interrupt pending bit. If SEIP is implemented and delegated to S-mode, it is read-only in sip; it is typically set and cleared by a platform interrupt controller.
The interrupt represented by SEIP is not pending.
The interrupt represented by SEIP is pending; delivery also depends on sie and sstatus.SIE.
Fixed-zero bits in the standard interrupt region; read as zero.
Reserved (bit 10) — Fixed-zero bits in the standard interrupt region; read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Restricted view of the machine external-interrupt pending bit. It is visible in sip only when writable mideleg[11] is set; otherwise it reads zero. The underlying mip.MEIP bit is read-only.
MEIP (bit 11) — Restricted view of the machine external-interrupt pending bit. It is visible in sip only when writable mideleg[11] is set; otherwise it reads zero. The underlying mip.MEIP bit is read-only.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bit in the standard interrupt region; reads as zero.
Reserved (bit 12) — Reserved bit in the standard interrupt region; reads as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Local counter-overflow interrupt-pending bit. With Sscofpmf it is read-write in sip and reflects local counter-overflow requests; without Sscofpmf it is read-only zero.
LCOFIP (bit 13) — Local counter-overflow interrupt-pending bit. With Sscofpmf it is read-write in sip and reflects local counter-overflow requests; without Sscofpmf it is read-only zero.
The interrupt represented by LCOFIP is not pending.
The interrupt represented by LCOFIP is pending; delivery also depends on sie and sstatus.SIE.
Fixed-zero bits in the standard interrupt region; read as zero.
Reserved (bits 15:14) — Fixed-zero bits in the standard interrupt region; read as zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Bits 16 and above are designated for platform use; each bit may be writable or read-only, and unimplemented interrupt bits are read-only zero.
Platform interrupt pending (bits SXLEN-1:16) — Bits 16 and above are designated for platform use; each bit may be writable or read-only, and unimplemented interrupt bits are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
sip is not a full mip mirror; it is the S-mode-visible pending-interrupt view for delegated interrupts. SSIP can be written by S-mode software; STIP/SEIP are read-only in sip; LCOFIP belongs to the Sscofpmf local counter-overflow interrupt.
Read/write sip using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8
sip is the restricted S-mode view of mip for S-mode-relevant pending bits such as SSIP, STIP, and SEIP. S-mode software can request or clear supervisor software interrupts through SSIP; STIP and SEIP reflect timer or external interrupt-controller state. sip works with sie: a source must be pending and enabled, and the current privilege state must allow S-mode interrupt delivery before the interrupt is taken.
SSIP(bit1) S-mode software interrupt pending | STIP(bit5) S-mode timer interrupt pending | SEIP(bit9) S-mode external interrupt pending
Read sip to observe pending interrupts delegated to S-mode.
Use the corresponding sie bit and sstatus.SIE to determine whether the interrupt can be delivered to S-mode.
Write or clear only pending bits that the specification or platform defines as writable.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sip as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
No. SSIP is writable when delegated to S-mode; STIP and SEIP are read-only in sip; LCOFIP is defined only with Sscofpmf and is cleared by software, and non-delegated bits read as zero in sip.