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CSR Bit Fields

RISC-V sip CSR Register

Address 0x144Privilege SupervisorAccess RW / XLENSupervisor status, trap, and interrupt CSRs

Supervisor interrupt-pending register; a view of mip bits relevant to S-mode.

The sip (Supervisor Interrupt Pending) CSR at address 0x144 is the S-mode restricted view of mip, showing S-mode-relevant pending interrupts such as SSIP, STIP, and SEIP. For a pending interrupt to be serviced while running in S-mode, the corresponding enable bit in sie must be set and sstatus.SIE must permit interrupt delivery.

Related Search Terms
sip CSRsip 0x144supervisor interrupt pendingsip SSIP STIP SEIPsip LCOFIPRISC-V sip bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:14Reserved0
Field Map

Understand sip By Bit Fields

4 key fields
1

SSIP

RW

Supervisor-mode Software Interrupt Pending

SSIP (bit 1) — Supervisor-mode Software Interrupt Pending.

What This Field Controls

  • - Supervisor-mode Software Interrupt Pending

Common Values

0Not pending

The interrupt represented by SSIP is not pending.

1Pending

The interrupt represented by SSIP is pending; delivery also depends on sie and sstatus.SIE.

5

STIP

RO

Supervisor-mode Timer Interrupt Pending

STIP (bit 5) — Supervisor-mode Timer Interrupt Pending.

What This Field Controls

  • - Supervisor-mode Timer Interrupt Pending

Common Values

0Not pending

The interrupt represented by STIP is not pending.

1Pending

The interrupt represented by STIP is pending; delivery also depends on sie and sstatus.SIE.

9

SEIP

RO

Supervisor-mode External Interrupt Pending

SEIP (bit 9) — Supervisor-mode External Interrupt Pending.

What This Field Controls

  • - Supervisor-mode External Interrupt Pending

Common Values

0Not pending

The interrupt represented by SEIP is not pending.

1Pending

The interrupt represented by SEIP is pending; delivery also depends on sie and sstatus.SIE.

13

LCOFIP

RO

Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

LCOFIP (bit 13) — Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

What This Field Controls

  • - Local counter-overflow interrupt pending; meaningful only when the local counter-overflow interrupt support is implemented.

Common Values

0Not pending

The interrupt represented by LCOFIP is not pending.

1Pending

The interrupt represented by LCOFIP is pending; delivery also depends on sie and sstatus.SIE.

Official Basis & Search Notes

sip is a RW CSR in supervisor status, trap, and interrupt csrs at 0x144. Check privilege and implemented extensions before interpreting its bit fields.

sip address, lowest access privilege, and access class are checked against the official CSR table: 0x144, Supervisor, RW.
Read it as part of supervisor status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

Assembly Operation Examples

Read/write sip using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, sip
Read S-mode interrupt pending status from S-mode
csrr t0, sip; andi t0, t0, 0x20; bnez t0, handle_stip
Check STIP(bit5) pending and handle

Relationship With Other CSRs

sip is the restricted S-mode view of mip for S-mode-relevant pending bits such as SSIP, STIP, and SEIP. S-mode software can request or clear supervisor software interrupts through SSIP; STIP and SEIP reflect timer or external interrupt-controller state. sip works with sie: a source must be pending and enabled, and the current privilege state must allow S-mode interrupt delivery before the interrupt is taken.

Key Bit Field Reference

SSIP(bit1) S-mode software interrupt pending | STIP(bit5) S-mode timer interrupt pending | SEIP(bit9) S-mode external interrupt pending

What To Check First When Reading This CSR

  • - First confirm that the current hart implements sip; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x144 and the lowest access privilege (Supervisor) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads sip to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can sip be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sip as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing sip?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.