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CSR Bit Fields

RISC-V sie CSR Register

Address 0x104Privilege SupervisorAccess RW / XLENSupervisor status, trap, and interrupt CSRs

Supervisor interrupt-enable register; a view of mie bits relevant to S-mode.

The sie (Supervisor Interrupt Enable) CSR at address 0x104 is the S-mode restricted view of mie. It controls S-mode-relevant interrupt sources: SSIE (bit 1), STIE (bit 5), and SEIE (bit 9). For an S-mode interrupt to be taken while running in S-mode, the source must be pending in sip, enabled in sie, and sstatus.SIE must permit interrupt delivery.

Related Search Terms
sie CSRsie 0x104supervisor interrupt enablesie SSIE STIE SEIEsie LCOFIERISC-V sie bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:14Reserved0
Field Map

Understand sie By Bit Fields

4 key fields
1

SSIE

RW

Supervisor-mode Software Interrupt Enable

SSIE (bit 1) — Supervisor-mode Software Interrupt Enable.

What This Field Controls

  • - Supervisor-mode Software Interrupt Enable

Common Values

0Disabled

The supervisor interrupt enabled by SSIE is disabled.

1Enabled

The supervisor interrupt enabled by SSIE is enabled; delivery also depends on sstatus.SIE and pending state.

5

STIE

RW

Supervisor-mode Timer Interrupt Enable

STIE (bit 5) — Supervisor-mode Timer Interrupt Enable.

What This Field Controls

  • - Supervisor-mode Timer Interrupt Enable

Common Values

0Disabled

The supervisor interrupt enabled by STIE is disabled.

1Enabled

The supervisor interrupt enabled by STIE is enabled; delivery also depends on sstatus.SIE and pending state.

9

SEIE

RW

Supervisor-mode External Interrupt Enable

SEIE (bit 9) — Supervisor-mode External Interrupt Enable.

What This Field Controls

  • - Supervisor-mode External Interrupt Enable

Common Values

0Disabled

The supervisor interrupt enabled by SEIE is disabled.

1Enabled

The supervisor interrupt enabled by SEIE is enabled; delivery also depends on sstatus.SIE and pending state.

13

LCOFIE

RW

Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

LCOFIE (bit 13) — Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

What This Field Controls

  • - Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

Common Values

0Disabled

The supervisor interrupt enabled by LCOFIE is disabled.

1Enabled

The supervisor interrupt enabled by LCOFIE is enabled; delivery also depends on sstatus.SIE and pending state.

Official Basis & Search Notes

sie is a RW CSR in supervisor status, trap, and interrupt csrs at 0x104. Check privilege and implemented extensions before interpreting its bit fields.

sie address, lowest access privilege, and access class are checked against the official CSR table: 0x104, Supervisor, RW.
Read it as part of supervisor status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

Assembly Operation Examples

Read/write sie using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, sie
Read enabled S-mode interrupt sources from S-mode
li t0, 0x00000022; csrs sie, t0
Enable STIE(bit5)+SSIE(bit1)

Relationship With Other CSRs

sie is the S-mode restricted view of mie for S-mode-relevant interrupt enable bits such as SSIE, STIE, and SEIE. It works with sstatus.SIE and sip: the source must be pending in sip, enabled in sie, and allowed by the current privilege/SIE state before the interrupt is taken.

Key Bit Field Reference

SSIE(bit1) S-mode software interrupt enable | STIE(bit5) S-mode timer interrupt enable | SEIE(bit9) S-mode external interrupt enable

What To Check First When Reading This CSR

  • - First confirm that the current hart implements sie; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x104 and the lowest access privilege (Supervisor) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads sie to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can sie be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sie as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing sie?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.