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CSR Bit Fields

RISC-V mie CSR Register

Address 0x304Privilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine interrupt-enable register; controls which interrupts can be taken in M-mode.

The mie (Machine Interrupt Enable) CSR at address 0x304 controls which interrupt sources are enabled. It provides enable bits such as SSIE, MSIE, STIE, MTIE, SEIE, and MEIE. Setting bits in mie alone is not sufficient: the corresponding pending bits in mip must be asserted, and interrupts taken in M-mode also depend on mstatus.MIE and delegation state.

Related Search Terms

mie CSR mie 0x304 machine interrupt enable mie MSIE MTIE MEIE mie LCOFIE RISC-V mie bits

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

PLATFORM63:16Platform-defined; RW/RO000RO0

PLATFORM63:16Platform-defined; RW/RO0 015:14RO0SSIE1RW/RO0 00RO0

Field Map

Understand mie By Bit Fields

16 key fields

XLEN-1:16

PLATFORM

Platform-defined; RW/RO0

Interrupt identities 16 and above are designated for platform use; a corresponding enable bit must be writable if that interrupt can ever become pending, otherwise it must be read-only zero.

PLATFORM (bits XLEN-1:16) — Interrupt identities 16 and above are designated for platform use; a corresponding enable bit must be writable if that interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Interrupt identities 16 and above are designated for platform use; a corresponding enable bit must be writable if that interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

15:14

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bits 15:14) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

LCOFIE

RW/RO0

Local counter-overflow interrupt enable defined by Sscofpmf; read-only zero when Sscofpmf is not implemented.

LCOFIE (bit 13) — Local counter-overflow interrupt enable defined by Sscofpmf; read-only zero when Sscofpmf is not implemented.

What This Field Controls

- Local counter-overflow interrupt enable defined by Sscofpmf; read-only zero when Sscofpmf is not implemented.

Common Values

0Disabled

The machine interrupt enabled by LCOFIE is disabled.

1Enabled

The machine interrupt enabled by LCOFIE is enabled; delivery also depends on mstatus plus pending/delegation state.

SGEIE / 0

RW/RO0 with H; otherwise RO0

Supervisor Guest External Interrupt Enable when H is implemented, aliasing hie.SGEIE; read-only zero without H.

SGEIE / 0 (bit 12) — Supervisor Guest External Interrupt Enable when H is implemented, aliasing hie.SGEIE; read-only zero without H.

What This Field Controls

- Supervisor Guest External Interrupt Enable when H is implemented, aliasing hie.SGEIE; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MEIE

RW/RO0

Machine-mode External Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

MEIE (bit 11) — Machine-mode External Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Machine-mode External Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by MEIE is disabled.

1Enabled

The machine interrupt enabled by MEIE is enabled; delivery also depends on mstatus plus pending/delegation state.

VSEIE / 0

RW/RO0 with H; otherwise RO0

Virtual Supervisor External Interrupt Enable when H is implemented, aliasing hie.VSEIE; read-only zero without H.

VSEIE / 0 (bit 10) — Virtual Supervisor External Interrupt Enable when H is implemented, aliasing hie.VSEIE; read-only zero without H.

What This Field Controls

- Virtual Supervisor External Interrupt Enable when H is implemented, aliasing hie.VSEIE; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

SEIE

RW/RO0

Supervisor external-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

SEIE (bit 9) — Supervisor external-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Supervisor external-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by SEIE is disabled.

1Enabled

The machine interrupt enabled by SEIE is enabled; delivery also depends on mstatus plus pending/delegation state.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 8) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MTIE

RW/RO0

Machine-mode Timer Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

MTIE (bit 7) — Machine-mode Timer Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Machine-mode Timer Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by MTIE is disabled.

1Enabled

The machine interrupt enabled by MTIE is enabled; delivery also depends on mstatus plus pending/delegation state.

VSTIE / 0

RW/RO0 with H; otherwise RO0

Virtual Supervisor Timer Interrupt Enable when H is implemented, aliasing hie.VSTIE; read-only zero without H.

VSTIE / 0 (bit 6) — Virtual Supervisor Timer Interrupt Enable when H is implemented, aliasing hie.VSTIE; read-only zero without H.

What This Field Controls

- Virtual Supervisor Timer Interrupt Enable when H is implemented, aliasing hie.VSTIE; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

STIE

RW/RO0

Supervisor timer-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

STIE (bit 5) — Supervisor timer-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Supervisor timer-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by STIE is disabled.

1Enabled

The machine interrupt enabled by STIE is enabled; delivery also depends on mstatus plus pending/delegation state.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 4) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

MSIE

RW/RO0

Machine-mode Software Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

MSIE (bit 3) — Machine-mode Software Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Machine-mode Software Interrupt Enable; it must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by MSIE is disabled.

1Enabled

The machine interrupt enabled by MSIE is enabled; delivery also depends on mstatus plus pending/delegation state.

VSSIE / 0

RW/RO0 with H; otherwise RO0

Virtual Supervisor Software Interrupt Enable when H is implemented, aliasing hie.VSSIE; read-only zero without H.

VSSIE / 0 (bit 2) — Virtual Supervisor Software Interrupt Enable when H is implemented, aliasing hie.VSSIE; read-only zero without H.

What This Field Controls

- Virtual Supervisor Software Interrupt Enable when H is implemented, aliasing hie.VSSIE; read-only zero without H.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

SSIE

RW/RO0

Supervisor software-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

SSIE (bit 1) — Supervisor software-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

What This Field Controls

- Supervisor software-interrupt enable; read-only zero when S-mode is not implemented. It must be writable when the corresponding interrupt can ever become pending, otherwise it must be read-only zero.

Common Values

0Disabled

The machine interrupt enabled by SSIE is disabled.

1Enabled

The machine interrupt enabled by SSIE is enabled; delivery also depends on mstatus plus pending/delegation state.

0

RO0

Fixed-zero bit in the standard interrupt-cause region.

0 (bit 0) — Fixed-zero bit in the standard interrupt-cause region.

What This Field Controls

- Fixed-zero bit in the standard interrupt-cause region.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mie is a RW CSR in machine status, trap, and interrupt csrs at 0x304. Check privilege and implemented extensions before interpreting its bit fields.

The official CSR table defines mie as the mandatory Machine RW CSR at 0x304.

Interrupt cause i corresponds to mie[i] and mip[i]; an M-mode interrupt trap also requires the pending, global-enable, and delegation conditions to be satisfied.

If an interrupt can ever become pending, its mie bit must be writable; otherwise the bit must be read-only zero. Interrupt identities 16 and above are designated for platform use.

RISC-V Privileged Architecture Manual - Machine-Level ISA (2026-07-09)

Assembly Operation Examples

Read/write mie using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, mie

Read currently enabled interrupt source bitmask

li t0, 0x00000088; csrs mie, t0

Enable MTIE(bit7)+MSIE(bit3)

li t0, 0x00000088; csrc mie, t0

Disable MTIE+MSIE (atomic clear)

# Enable machine timer interrupt — complete flow

Enable machine timer interrupt — complete flow

li t0, 0x80; csrs mie, t0

step 1: set MTIE(bit7)=1 in mie to enable timer interrupt source

li t0, 0x08; csrs mstatus, t0

step 2: set mstatus.MIE(bit3)=1 for global interrupt enable

csrr t0, mip; andi t0, t0, 0x80; bnez t0, handle_mtip

step 3: poll mip.MTIP(bit7) — only handle when timer interrupt is pending

Relationship With Other CSRs

mie controls whether individual interrupt sources are enabled. For interrupts taken in M-mode, mstatus.MIE must also allow global interrupts; interrupts delegated to S-mode follow the sstatus.SIE plus sie/sip rules. mip indicates pending interrupt requests. sie is the restricted S-mode view of mie. Common interrupt bits include MSIE(bit3), MTIE(bit7), MEIE(bit11), SSIE(bit1), STIE(bit5), and SEIE(bit9); local counter-overflow interrupts use LCOFIE/LCOFIP(bit13) when the relevant support is implemented.

Key Bit Field Reference

What To Check First When Reading This CSR

- mie is the mandatory MXLEN-bit machine interrupt-enable CSR at 0x304; a direct access below M-mode raises an illegal-instruction exception.
- Bit i corresponds to interrupt cause i in mcause; interpret it together with the pending bit in mip and the delegation bit in mideleg.
- A non-writable mie bit must read as zero; the CSR-level RW classification does not make every bit writable.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads mie to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mie be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mie as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mie?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.