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CSR Bit Fields

RISC-V mie CSR Register

Address 0x304Privilege MachineAccess RW / XLENMachine status, trap, and interrupt CSRs

Machine interrupt-enable register; controls which interrupts can be taken in M-mode.

The mie (Machine Interrupt Enable) CSR at address 0x304 controls which interrupt sources are enabled. It provides enable bits such as SSIE, MSIE, STIE, MTIE, SEIE, and MEIE. Setting bits in mie alone is not sufficient: the corresponding pending bits in mip must be asserted, and interrupts taken in M-mode also depend on mstatus.MIE and delegation state.

Related Search Terms
mie CSRmie 0x304machine interrupt enablemie MSIE MTIE MEIEmie LCOFIERISC-V mie bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:14Reserved0
Field Map

Understand mie By Bit Fields

7 key fields
1

SSIE

RW

Supervisor-mode Software Interrupt Enable

SSIE (bit 1) — Supervisor-mode Software Interrupt Enable.

What This Field Controls

  • - Supervisor-mode Software Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by SSIE is disabled.

1Enabled

The machine interrupt enabled by SSIE is enabled; delivery also depends on mstatus plus pending/delegation state.

3

MSIE

RW

Machine-mode Software Interrupt Enable

MSIE (bit 3) — Machine-mode Software Interrupt Enable.

What This Field Controls

  • - Machine-mode Software Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by MSIE is disabled.

1Enabled

The machine interrupt enabled by MSIE is enabled; delivery also depends on mstatus plus pending/delegation state.

5

STIE

RW

Supervisor-mode Timer Interrupt Enable

STIE (bit 5) — Supervisor-mode Timer Interrupt Enable.

What This Field Controls

  • - Supervisor-mode Timer Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by STIE is disabled.

1Enabled

The machine interrupt enabled by STIE is enabled; delivery also depends on mstatus plus pending/delegation state.

7

MTIE

RW

Machine-mode Timer Interrupt Enable

MTIE (bit 7) — Machine-mode Timer Interrupt Enable.

What This Field Controls

  • - Machine-mode Timer Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by MTIE is disabled.

1Enabled

The machine interrupt enabled by MTIE is enabled; delivery also depends on mstatus plus pending/delegation state.

9

SEIE

RW

Supervisor-mode External Interrupt Enable

SEIE (bit 9) — Supervisor-mode External Interrupt Enable.

What This Field Controls

  • - Supervisor-mode External Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by SEIE is disabled.

1Enabled

The machine interrupt enabled by SEIE is enabled; delivery also depends on mstatus plus pending/delegation state.

11

MEIE

RW

Machine-mode External Interrupt Enable

MEIE (bit 11) — Machine-mode External Interrupt Enable.

What This Field Controls

  • - Machine-mode External Interrupt Enable

Common Values

0Disabled

The machine interrupt enabled by MEIE is disabled.

1Enabled

The machine interrupt enabled by MEIE is enabled; delivery also depends on mstatus plus pending/delegation state.

13

LCOFIE

RW

Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

LCOFIE (bit 13) — Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

What This Field Controls

  • - Local counter-overflow interrupt enable; meaningful only when the local counter-overflow interrupt support is implemented.

Common Values

0Disabled

The machine interrupt enabled by LCOFIE is disabled.

1Enabled

The machine interrupt enabled by LCOFIE is enabled; delivery also depends on mstatus plus pending/delegation state.

Official Basis & Search Notes

mie is a RW CSR in machine status, trap, and interrupt csrs at 0x304. Check privilege and implemented extensions before interpreting its bit fields.

mie address, lowest access privilege, and access class are checked against the official CSR table: 0x304, Machine, RW.
Read it as part of machine status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

Assembly Operation Examples

Read/write mie using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8

csrr t0, mie
Read currently enabled interrupt source bitmask
li t0, 0x00000088; csrs mie, t0
Enable MTIE(bit7)+MSIE(bit3)
li t0, 0x00000088; csrc mie, t0
Disable MTIE+MSIE (atomic clear)
# Enable machine timer interrupt — complete flow
Enable machine timer interrupt — complete flow
li t0, 0x80; csrs mie, t0
step 1: set MTIE(bit7)=1 in mie to enable timer interrupt source
li t0, 0x08; csrs mstatus, t0
step 2: set mstatus.MIE(bit3)=1 for global interrupt enable
csrr t0, mip; andi t0, t0, 0x80; bnez t0, handle_mtip
step 3: poll mip.MTIP(bit7) — only handle when timer interrupt is pending

Relationship With Other CSRs

mie controls whether individual interrupt sources are enabled. For interrupts taken in M-mode, mstatus.MIE must also allow global interrupts; interrupts delegated to S-mode follow the sstatus.SIE plus sie/sip rules. mip indicates pending interrupt requests. sie is the restricted S-mode view of mie. Common interrupt bits include MSIE(bit3), MTIE(bit7), MEIE(bit11), SSIE(bit1), STIE(bit5), and SEIE(bit9); local counter-overflow interrupts use LCOFIE/LCOFIP(bit13) when the relevant support is implemented.

Key Bit Field Reference

SSIE(bit1) S-mode software | MSIE(bit3) M-mode software | STIE(bit5) S-mode timer | MTIE(bit7) M-mode timer | SEIE(bit9) S-mode external | MEIE(bit11) M-mode external | LCOFIE(bit13) local counter-overflow interrupt enable (conditional)

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mie; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x304 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mie to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mie be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mie as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mie?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.