Machine-mode status register containing global interrupt enables, privilege-level stack, and extension state control fields.
The mstatus (Machine Status) CSR at address 0x300 is the central global state register in RISC-V machine mode. It controls the global interrupt enable (MIE, bit 3), saves pre-trap interrupt state (MPIE, bit 7), records the previous privilege level for trap return (MPP, bits 12:11), and manages floating-point, vector, and extension context state through FS/VS/XS. The SD bit at XLEN-1 summarizes whether any FS, VS, or XS state is dirty. mstatus is essential for trap handling, privilege switching, and context-switch optimization.
State-dirty summary bit; set when FS, VS, or XS is Dirty. In RV32 this appears at bit 31.
SD (bit 63) — State-dirty summary bit; set when FS, VS, or XS is Dirty. In RV32 this appears at bit 31.
No FS, VS, or XS field is Dirty.
At least one of FS, VS, or XS is Dirty.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bits 62:43) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
M-mode-disable-trap bit (Smdbltrp); controls unexpected/double-trap behavior during sensitive M-mode trap phases. Explicitly writing it to 1 clears MIE; MRET/SRET executed in M-mode clears it.
MDT (bit 42) — M-mode-disable-trap bit (Smdbltrp); controls unexpected/double-trap behavior during sensitive M-mode trap phases. Explicitly writing it to 1 clears MIE; MRET/SRET executed in M-mode clears it.
Machine double-trap guard is not set.
Machine double-trap guard is set; later M-mode traps follow Smdbltrp rules.
Machine Previous Expected Landing Pad state defined by Zicfilp. A trap into M-mode saves the previous ELP here; MRET restores ELP according to the target privilege mode's LPE and then clears this field to NO_LP_EXPECTED.
MPELP (bit 41) — Machine Previous Expected Landing Pad state defined by Zicfilp. A trap into M-mode saves the previous ELP here; MRET restores ELP according to the target privilege mode's LPE and then clears this field to NO_LP_EXPECTED.
No landing-pad instruction is expected.
A landing-pad instruction is expected.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bit 40) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Machine Previous Virtualization mode defined by the Hypervisor extension; records V before a trap into M-mode. This field does not exist without the Hypervisor extension.
MPV (bit 39) — Machine Previous Virtualization mode defined by the Hypervisor extension; records V before a trap into M-mode. This field does not exist without the Hypervisor extension.
Execution before the M-mode trap was not virtualized.
Execution before the M-mode trap was virtualized.
Guest Virtual Address flag defined by the Hypervisor extension; indicates whether the address written to mtval is a guest virtual address. This field does not exist without the Hypervisor extension.
GVA (bit 38) — Guest Virtual Address flag defined by the Hypervisor extension; indicates whether the address written to mtval is a guest virtual address. This field does not exist without the Hypervisor extension.
The address in mtval is not a guest virtual address.
The address in mtval is a guest virtual address.
Machine Big-Endian control. When MPRV=0, it controls non-instruction-fetch memory accesses made from M-mode; instruction fetches are always little-endian. SBE and UBE may be read-only copies of MBE.
MBE (bit 37) — Machine Big-Endian control. When MPRV=0, it controls non-instruction-fetch memory accesses made from M-mode; instruction fetches are always little-endian. SBE and UBE may be read-only copies of MBE.
When MPRV=0, non-instruction-fetch M-mode memory accesses are little-endian; instruction fetch is always little-endian.
When MPRV=0, non-instruction-fetch M-mode memory accesses are big-endian; instruction fetch remains little-endian.
S-mode data endianness control; 0 is little-endian and 1 is big-endian, while instruction fetch remains little-endian.
SBE (bit 36) — S-mode data endianness control; 0 is little-endian and 1 is big-endian, while instruction fetch remains little-endian.
S-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
S-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
Effective XLEN encoding for S-mode on RV64; read-only zero if S-mode is not implemented.
SXL (bits 35:34) — Effective XLEN encoding for S-mode on RV64; read-only zero if S-mode is not implemented.
Effective XLEN is 32.
Effective XLEN is 64.
Reserved encoding; portable software must not write or depend on it.
Effective XLEN encoding for U-mode on RV64; read-only zero if U-mode is not implemented.
UXL (bits 33:32) — Effective XLEN encoding for U-mode on RV64; read-only zero if U-mode is not implemented.
Effective XLEN is 32.
Effective XLEN is 64.
Reserved encoding; portable software must not write or depend on it.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bits 31:25) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
S-mode-disable-trap bit defined by Ssdbltrp. Explicitly writing 1 clears SIE; a trap into S-mode sets it when it was 0, while a trap with it already set follows the double-trap rules; SRET clears it. It is read-only zero when Ssdbltrp is not implemented.
SDT (bit 24) — S-mode-disable-trap bit defined by Ssdbltrp. Explicitly writing 1 clears SIE; a trap into S-mode sets it when it was 0, while a trap with it already set follows the double-trap rules; SRET clears it. It is read-only zero when Ssdbltrp is not implemented.
The S-mode double-trap guard is clear.
The S-mode double-trap guard is set.
S-mode Previous Expected Landing Pad state defined by Zicfilp. A trap into S/HS-mode saves the previous ELP here; SRET restores ELP according to the target privilege mode's LPE and then clears this field to NO_LP_EXPECTED.
SPELP (bit 23) — S-mode Previous Expected Landing Pad state defined by Zicfilp. A trap into S/HS-mode saves the previous ELP here; SRET restores ELP according to the target privilege mode's LPE and then clears this field to NO_LP_EXPECTED.
No landing-pad instruction is expected.
A landing-pad instruction is expected.
When set, SRET executed in S-mode traps to M-mode.
TSR (bit 22) — When set, SRET executed in S-mode traps to M-mode.
S-mode SRET does not trap because of TSR.
S-mode SRET raises an illegal-instruction exception.
When set, lower-privilege WFI raises an illegal-instruction exception if it does not complete within an implementation-specific bounded time; an implementation may raise the exception immediately.
TW (bit 21) — When set, lower-privilege WFI raises an illegal-instruction exception if it does not complete within an implementation-specific bounded time; an implementation may raise the exception immediately.
Lower-privilege WFI is not forced to trap because of TW.
Lower-privilege WFI raises an illegal-instruction exception if it does not complete within the implementation-specific bounded time.
When set, S-mode accesses to satp or execution of SFENCE.VMA/SINVAL.VMA raise an illegal-instruction exception; read-only zero when S-mode is not implemented.
TVM (bit 20) — When set, S-mode accesses to satp or execution of SFENCE.VMA/SINVAL.VMA raise an illegal-instruction exception; read-only zero when S-mode is not implemented.
S-mode may access satp and execute address-translation fences under the usual rules.
S-mode accesses to satp or SFENCE.VMA/SINVAL.VMA trap.
Allows loads from executable pages.
MXR (bit 19) — Allows loads from executable pages.
Loads do not read a page merely because it is executable.
Loads may read from executable pages.
Allows S-mode to access U-mode pages.
SUM (bit 18) — Allows S-mode to access U-mode pages.
S-mode cannot access pages with U=1 unless another architectural rule permits it.
S-mode may access pages with U=1, while instruction fetch remains constrained by the specification.
Data memory accesses use the effective privilege specified by MPP.
MPRV (bit 17) — Data memory accesses use the effective privilege specified by MPP.
Data memory accesses use the current privilege mode.
Data memory accesses use the effective privilege mode specified by MPP.
Additional user-extension state status.
XS (bits 16:15) — Additional user-extension state status.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Floating-point state status.
FS (bits 14:13) — Floating-point state status.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Privilege mode before entering the M-mode trap.
MPP (bits 12:11) — Privilege mode before entering the M-mode trap.
Previous privilege mode before the M-mode trap was User.
Previous privilege mode before the M-mode trap was Supervisor.
This encoding is reserved; portable software must not write or depend on it.
Previous privilege mode before the M-mode trap was Machine.
Vector state status; controls availability of vector instructions/vector CSRs and tracks dirty state.
VS (bits 10:9) — Vector state status; controls availability of vector instructions/vector CSRs and tracks dirty state.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Privilege mode before entering the S-mode trap.
SPP (bit 8) — Privilege mode before entering the S-mode trap.
Previous privilege mode before the S-mode trap was User.
Previous privilege mode before the S-mode trap was Supervisor.
Saved MIE value before entering an M-mode trap.
MPIE (bit 7) — Saved MIE value before entering an M-mode trap.
MIE was 0 before the M-mode trap, or the saved post-return interrupt state is disabled.
MIE was 1 before the M-mode trap and MRET can restore it under the rules.
U-mode explicit load/store endianness control; 0=little-endian, 1=big-endian. It is read-only zero if U-mode is not implemented and may be a read-only copy of MBE or SBE.
UBE (bit 6) — U-mode explicit load/store endianness control; 0=little-endian, 1=big-endian. It is read-only zero if U-mode is not implemented and may be a read-only copy of MBE or SBE.
U-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
U-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
Saved SIE value before entering an S-mode trap; read-only zero if S-mode is not implemented.
SPIE (bit 5) — Saved SIE value before entering an S-mode trap; read-only zero if S-mode is not implemented.
SIE was 0 before the S-mode trap, or the saved post-return interrupt state is disabled.
SIE was 1 before the S-mode trap and SRET can restore it under the rules.
Reserved WPRI (Writes Preserve, Reads Ignore).
WPRI (bit 4) — Reserved WPRI (Writes Preserve, Reads Ignore).
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Global interrupt enable for M-mode.
MIE (bit 3) — Global interrupt enable for M-mode.
When currently running in M-mode, global machine interrupts are disabled.
When currently running in M-mode, global machine interrupts are enabled; delivery also depends on mie/mip and delegation state.
Reserved WPRI.
WPRI (bit 2) — Reserved WPRI.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Global interrupt enable for S-mode; read-only zero if S-mode is not implemented.
SIE (bit 1) — Global interrupt enable for S-mode; read-only zero if S-mode is not implemented.
When currently running in S-mode, global supervisor interrupts are disabled.
When currently running in S-mode, global supervisor interrupts are enabled; delivery also depends on sie/sip and delegation state.
Reserved WPRI (Writes Preserve, Reads Ignore).
WPRI (bit 0) — Reserved WPRI (Writes Preserve, Reads Ignore).
This field is better understood together with surrounding context than as a fixed memorized enumeration.
mstatus is a RW CSR in machine status, trap, and interrupt csrs at 0x300. Check privilege and implemented extensions before interpreting its bit fields.
Read/write mstatus using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8
mstatus is the core M-mode status register. sstatus is the restricted view of S-mode-relevant mstatus fields, including SIE, SPIE, SPP, SUM, and MXR. mstatus.MIE controls global interrupt enable for M-mode; M-mode interrupt delivery also depends on mie/mip and delegation state. FS/VS/XS fields control FP/vector/extension register context save policy.
MIE(bit3) global interrupt enable | MPIE(bit7) saved MIE before trap | MPP(bits12:11) pre-trap privilege (00=U,01=S,11=M) | FS(bits14:13) FPU state (00=Off,01=Initial,10=Clean,11=Dirty) | SD(XLEN-1; RV64 bit63, RV32 bit31) state dirty summary (set when FS, VS, or XS is Dirty)
During initialization or the relevant privileged flow, software reads mstatus to observe the current state.
Modify only the target fields while preserving all other bits.
Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mstatus as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.