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CSR Bit Fields

RISC-V mtvec CSR Register

Address 0x305Privilege MachineAccess WARL RW / MXLENMachine status, trap, and interrupt CSRs

Machine trap-vector base-address register; holds the entry address of the M-mode trap handler.

Related Search Terms
mtvec CSRmtvec 0x305machine trap vectormtvec BASE MODEM-mode trap handlerRISC-V mtvec
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
BASE63:2WARLMODE1:0WARL
Field Map

Understand mtvec By Bit Fields

2 key fields
1:0

MODE

WARL

Vectoring mode select: 0=Direct, 1=Vectored; other standard encodings are reserved unless defined by an extension.

MODE (bits 1:0) — Vectoring mode select: 0=Direct, 1=Vectored; other standard encodings are reserved unless defined by an extension.

What This Field Controls

  • - Vectoring mode select: 0=Direct, 1=Vectored; other standard encodings are reserved unless defined by an extension.

Common Values

0Direct

All synchronous exceptions and interrupts set pc to BASE.

1Vectored

Synchronous exceptions set pc to BASE; interrupts set pc to BASE + 4 x cause.

>=2Reserved

Reserved encoding; portable software must not write or depend on it.

XLEN-1:2

BASE

WARL

Trap-entry base-address field; the actual BASE is at least 4-byte aligned, and MODE may impose stricter alignment constraints.

BASE (bits XLEN-1:2) — Trap-entry base-address field; the actual BASE is at least 4-byte aligned, and MODE may impose stricter alignment constraints.

What This Field Controls

  • - Trap-entry base-address field; the actual BASE is at least 4-byte aligned, and MODE may impose stricter alignment constraints.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtvec is an MXLEN-bit WARL read/write machine trap-vector configuration CSR containing BASE and MODE; an implementation may make it hold a read-only value.

mtvec address, lowest access privilege, and access class are checked against the official CSR table and Machine trap-vector section: 0x305, Machine, WARL RW.
In Direct mode, all traps into M-mode set pc to BASE; in Vectored mode, synchronous exceptions go to BASE and interrupts go to BASE + 4*cause.
BASE is at least 4-byte aligned; MODE may impose stricter alignment constraints on BASE.
RISC-V Privileged Architecture Manual - Machine-Level ISA (2026-07-09)

What To Check First When Reading This CSR

  • - mtvec is the mandatory MXLEN-bit WARL CSR at 0x305; an implementation may make it a read-only value.
  • - Interpret MODE and BASE together: Direct mode sends every trap to BASE, while Vectored mode sends interrupts to BASE + 4×cause.
  • - BASE is at least four-byte aligned, and some MODE settings may impose stricter alignment.

Risk Checks Before Writing

  • - Align BASE for the target MODE before writing; an implementation can reject unsupported MODE/address combinations by selecting a legal WARL value.
  • - Read mtvec back to confirm the BASE and MODE actually accepted, and do not use reserved MODE encodings in portable software.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mtvec to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mtvec be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mtvec as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtvec?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.