RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mtvec CSR Register

Address 0x305Privilege MachineAccess RW / XLENMachine status, trap, and interrupt CSRs

Machine trap-vector base-address register; holds the entry address of the M-mode trap handler.

Related Search Terms
mtvec CSRmtvec 0x305machine trap vectormtvec BASE MODEM-mode trap handlerRISC-V mtvec
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
BASE63:2RWMODE1:0RW
Field Map

Understand mtvec By Bit Fields

2 key fields
1:0

MODE

RW

0=Direct mode, 1=Vectored mode

MODE (bits 1:0) — 0=Direct mode, 1=Vectored mode.

What This Field Controls

  • - 0=Direct mode, 1=Vectored mode

Common Values

0Direct

All synchronous exceptions and interrupts set pc to BASE.

1Vectored

Synchronous exceptions set pc to BASE; interrupts set pc to BASE + 4 x cause.

>=2Reserved

Reserved encoding; portable software must not write or depend on it.

XLEN-1:2

BASE

RW

Trap handler base address (4-byte aligned)

BASE (bits XLEN-1:2) — Trap handler base address (4-byte aligned).

What This Field Controls

  • - Trap handler base address (4-byte aligned)

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtvec is a RW CSR in machine status, trap, and interrupt csrs at 0x305. Check privilege and implemented extensions before interpreting its bit fields.

mtvec address, lowest access privilege, and access class are checked against the official CSR table: 0x305, Machine, RW.
Read it as part of machine status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mtvec; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x305 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mtvec to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mtvec be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mtvec as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtvec?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.