RISC-V mtval CSR Register

Address 0x343Privilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine trap-value CSR; when a trap enters M-mode, it holds either zero or exception-specific additional information.

Related Search Terms

mtval CSR mtval 0x343 machine trap value mtval fault address mtval illegal instruction RISC-V mtval

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0WARL or RO0

Field Map

Understand mtval By Bit Fields

1 key fields

MXLEN-1:0

VALUE

WARL or RO0

Additional trap value. If the platform specifies that no exceptions write a nonzero mtval, this CSR may be read-only zero, except that it must not be read-only zero when H is implemented; otherwise it is WARL and must hold all valid virtual addresses and zero, and when illegal-instruction bit return is supported, values below 2^min(MXLEN, ILEN).

VALUE (bits MXLEN-1:0) — Additional trap value. If the platform specifies that no exceptions write a nonzero mtval, this CSR may be read-only zero, except that it must not be read-only zero when H is implemented; otherwise it is WARL and must hold all valid virtual addresses and zero, and when illegal-instruction bit return is supported, values below 2^min(MXLEN, ILEN).

What This Field Controls

- Additional trap value. If the platform specifies that no exceptions write a nonzero mtval, this CSR may be read-only zero, except that it must not be read-only zero when H is implemented; otherwise it is WARL and must hold all valid virtual addresses and zero, and when illegal-instruction bit return is supported, values below 2^min(MXLEN, ILEN).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtval is the MXLEN-bit machine trap-value CSR at 0x343. On entry to an M-mode trap, it holds zero or exception-specific additional information; whether it is nonzero and what it means must be determined first from mcause and platform rules.

The official CSR table lists mtval at 0x343 with Machine-mode read/write access.

When a trap enters M-mode, mtval is written with zero or exception-specific information; the hardware platform specifies which exceptions must, may, or need not provide nonzero values.

If it is not read-only zero, mtval is WARL and must hold all valid virtual addresses and zero; mtval must not be read-only zero when H is implemented.

RISC-V Privileged Architecture Manual v20260120 RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

- mtval is an MXLEN-bit Machine-mode CSR at 0x343.
- When a trap enters M-mode, mtval is set to zero or written with exception-specific information; the hardware platform specifies which exceptions provide meaningful nonzero values.
- Determine the trap type from mcause before interpreting mtval.

Risk Checks Before Writing

- If mtval is not read-only zero, it is WARL; an implementation may convert an invalid address into another invalid address it can hold before writing it.
- Do not assume every exception writes a nonzero mtval; for other traps, mtval is set to zero.

Put It Back Into A Real Flow

The trap handler first reads mcause to identify the exception type.

If that exception type and platform may provide mtval information, read mtval.

Interpret mtval according to the exception type: faulting virtual address, illegal-instruction bits, software-check cause, or zero.

FAQ

Can mtval be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR table gives the lowest access privilege; mtval is at 0x343 with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtval?

When writing mtval, first confirm it is not read-only zero and follow WARL rules. When reading mtval, do not interpret it without mcause: the same value may represent an address, instruction bits, a software-check cause, or simply no additional information.