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CSR Bit Fields

RISC-V mcause CSR Register

Address 0x342Privilege MachineAccess RW / XLENMachine status, trap, and interrupt CSRs

Machine trap cause register; records the event type and cause code that triggered a trap.

Related Search Terms
mcause CSRmcause 0x342machine trap causemcause exception codemcause interrupt bitRISC-V mcause
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63WLRLException Code62:0WLRL
Field Map

Understand mcause By Bit Fields

2 key fields
XLEN-1

Interrupt

WLRL

1=Interrupt, 0=Exception; handled as part of the WLRL cause value.

Interrupt (bits XLEN-1) — 1=Interrupt, 0=Exception; handled as part of the WLRL cause value.

What This Field Controls

  • - 1=Interrupt, 0=Exception; handled as part of the WLRL cause value.

Common Values

00

This is a synchronous exception; the low field is interpreted as an exception cause code.

11

This is an interrupt; the low field is interpreted as an interrupt cause code.

XLEN-2:0

Exception Code

WLRL

Cause code; software must not assume that arbitrary written cause codes are retained, and must interpret only official and implemented legal values.

Exception Code (bits XLEN-2:0) — Cause code; software must not assume that arbitrary written cause codes are retained, and must interpret only official and implemented legal values.

What This Field Controls

  • - Cause code; software must not assume that arbitrary written cause codes are retained, and must interpret only official and implemented legal values.

Common Values

Synchronous exceptions
0Instruction address misaligned

Synchronous exception cause code 0.

1Instruction access fault

Synchronous exception cause code 1.

2Illegal instruction

Synchronous exception cause code 2.

3Breakpoint

Synchronous exception cause code 3.

4Load address misaligned

Synchronous exception cause code 4.

5Load access fault

Synchronous exception cause code 5.

6Store/AMO address misaligned

Synchronous exception cause code 6.

7Store/AMO access fault

Synchronous exception cause code 7.

8Environment call from U-mode

Synchronous exception cause code 8.

9Environment call from S-mode

Synchronous exception cause code 9.

11Environment call from M-mode

Synchronous exception cause code 11.

12Instruction page fault

Synchronous exception cause code 12.

13Load page fault

Synchronous exception cause code 13.

15Store/AMO page fault

Synchronous exception cause code 15.

16Double trap

Synchronous exception cause code 16, defined by the Smdbltrp extension.

18Software check

Synchronous exception cause code 18.

19Hardware error

Synchronous exception cause code 19.

Interrupts
1Supervisor software interrupt

When Interrupt is 1, low cause code 1 indicates a supervisor software interrupt.

3Machine software interrupt

When Interrupt is 1, low cause code 3 indicates a machine software interrupt.

5Supervisor timer interrupt

When Interrupt is 1, low cause code 5 indicates a supervisor timer interrupt.

7Machine timer interrupt

When Interrupt is 1, low cause code 7 indicates a machine timer interrupt.

9Supervisor external interrupt

When Interrupt is 1, low cause code 9 indicates a supervisor external interrupt.

11Machine external interrupt

When Interrupt is 1, low cause code 11 indicates a machine external interrupt.

13Counter-overflow interrupt

When Interrupt is 1, low cause code 13 indicates a counter-overflow interrupt.

Official Basis & Search Notes

mcause is a RW CSR in machine status, trap, and interrupt csrs at 0x342. Check privilege and implemented extensions before interpreting its bit fields.

mcause address, lowest access privilege, and access class are checked against the official CSR table: 0x342, Machine, RW.
Read it as part of machine status, trap, and interrupt csrs before interpreting the bit-field table on this page.
Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mcause; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x342 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mcause to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mcause be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mcause as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcause?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.