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CSR Bit Fields

RISC-V mcause CSR Register

Address 0x342Privilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine trap cause register; records the event type and cause code that triggered a trap.

Related Search Terms
mcause CSRmcause 0x342machine trap causemcause exception codemcause interrupt bitRISC-V mcause
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63RWException Code62:0WLRL
Field Map

Understand mcause By Bit Fields

2 key fields
XLEN-1

Interrupt

RW

Set to 1 when the trap was caused by an interrupt; 0 for a synchronous exception.

Interrupt (bits XLEN-1) — Set to 1 when the trap was caused by an interrupt; 0 for a synchronous exception.

What This Field Controls

  • - Set to 1 when the trap was caused by an interrupt; 0 for a synchronous exception.

Common Values

00

This is a synchronous exception; the low field is interpreted as an exception cause code.

11

This is an interrupt; the low field is interpreted as an interrupt cause code.

XLEN-2:0

Exception Code

WLRL

Code identifying the last exception or interrupt. This field is WLRL and is guaranteed to hold only supported exception codes; reserved, platform, custom, or extension-related encodings must be interpreted using the applicable official table.

Exception Code (bits XLEN-2:0) — Code identifying the last exception or interrupt. This field is WLRL and is guaranteed to hold only supported exception codes; reserved, platform, custom, or extension-related encodings must be interpreted using the applicable official table.

What This Field Controls

  • - Code identifying the last exception or interrupt. This field is WLRL and is guaranteed to hold only supported exception codes; reserved, platform, custom, or extension-related encodings must be interpreted using the applicable official table.

Common Values

Synchronous exceptions
0Instruction address misaligned

Synchronous exception cause code 0.

1Instruction access fault

Synchronous exception cause code 1.

2Illegal instruction

Synchronous exception cause code 2.

3Breakpoint

Synchronous exception cause code 3.

4Load address misaligned

Synchronous exception cause code 4.

5Load access fault

Synchronous exception cause code 5.

6Store/AMO address misaligned

Synchronous exception cause code 6.

7Store/AMO access fault

Synchronous exception cause code 7.

8Environment call from U-mode

Synchronous exception cause code 8.

9Environment call from S-mode

Synchronous exception cause code 9.

11Environment call from M-mode

Synchronous exception cause code 11.

12Instruction page fault

Synchronous exception cause code 12.

13Load page fault

Synchronous exception cause code 13.

15Store/AMO page fault

Synchronous exception cause code 15.

16Double trap

Synchronous exception cause code 16, defined by the Smdbltrp extension.

18Software check

Synchronous exception cause code 18.

19Hardware error

Synchronous exception cause code 19.

Interrupts
1Supervisor software interrupt

When Interrupt is 1, low cause code 1 indicates a supervisor software interrupt.

3Machine software interrupt

When Interrupt is 1, low cause code 3 indicates a machine software interrupt.

5Supervisor timer interrupt

When Interrupt is 1, low cause code 5 indicates a supervisor timer interrupt.

7Machine timer interrupt

When Interrupt is 1, low cause code 7 indicates a machine timer interrupt.

9Supervisor external interrupt

When Interrupt is 1, low cause code 9 indicates a supervisor external interrupt.

11Machine external interrupt

When Interrupt is 1, low cause code 11 indicates a machine external interrupt.

13Counter-overflow interrupt

When Interrupt is 1, low cause code 13 indicates a counter-overflow interrupt.

Official Basis & Search Notes

mcause is the MXLEN-bit Machine-mode trap-cause CSR at 0x342. The top Interrupt bit distinguishes interrupts from synchronous exceptions, and the low Exception Code is WLRL, guaranteed only to hold supported cause codes.

The official CSR table lists mcause at 0x342 with Machine-mode read/write access.
When a trap enters M-mode, hardware writes mcause with a code for the event that caused the trap.
Exception Code is WLRL; the standard table also reserves some encodings and designates some interrupt encodings for platform use.
RISC-V Privileged Architecture Manual v20260120RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

  • - mcause is an MXLEN-bit Machine-mode read/write CSR at 0x342.
  • - When a trap is taken into M-mode, hardware writes a cause code for the event; otherwise hardware never writes mcause.
  • - Check the top Interrupt bit first, then interpret the low Exception Code using the official cause-code table. Exception Code is WLRL.

Risk Checks Before Writing

  • - Software may explicitly write mcause, but Exception Code is WLRL and is guaranteed to retain only legal cause codes supported by the implementation.
  • - Do not interpret reserved, platform-use, or custom encodings as standard exceptions unless the applicable official extension or platform specification defines them.

Put It Back Into A Real Flow

1

The trap handler reads mcause.

2

Check the Interrupt bit: 1 means an interrupt cause code, 0 means a synchronous exception cause code.

3

Look up Exception Code in the applicable official cause-code table and combine it with mepc/mtval and related CSRs for dispatch.

FAQ

Can mcause be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR table gives the lowest access privilege; mcause is at 0x342 with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mcause?

When writing mcause, do not assume arbitrary cause codes are retained. Exception Code is WLRL and is guaranteed only to hold legal supported cause codes; after reading it, interpret it with the Interrupt bit and the official cause-code table.