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CSR Bit Fields

RISC-V scause CSR Register

Address 0x142Privilege SupervisorAccess RW / SXLENSupervisor status, trap, and interrupt CSRs

Supervisor trap cause register; records the interrupt bit and exception or interrupt cause code for an S-mode trap.

Related Search Terms
scause CSRscause 0x142supervisor trap causescause exception codescause interrupt bitRISC-V scause
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63RWException Code62:0WLRL
Field Map

Understand scause By Bit Fields

2 key fields
SXLEN-1

Interrupt

RW

Most-significant bit indicating whether the trap cause is an interrupt: 1=interrupt, 0=synchronous exception.

Interrupt (bits SXLEN-1) — Most-significant bit indicating whether the trap cause is an interrupt: 1=interrupt, 0=synchronous exception.

What This Field Controls

  • - Most-significant bit indicating whether the trap cause is an interrupt: 1=interrupt, 0=synchronous exception.

Common Values

00

This is a synchronous exception; the low field is interpreted as an exception cause code.

11

This is an interrupt; the low field is interpreted as an interrupt cause code.

SXLEN-2:0

Exception Code

WLRL

Exception or interrupt cause code. This field is WLRL and must hold values 0-31; interrupt codes are interpreted as supervisor interrupt causes.

Exception Code (bits SXLEN-2:0) — Exception or interrupt cause code. This field is WLRL and must hold values 0-31; interrupt codes are interpreted as supervisor interrupt causes.

What This Field Controls

  • - Exception or interrupt cause code. This field is WLRL and must hold values 0-31; interrupt codes are interpreted as supervisor interrupt causes.

Common Values

Synchronous exceptions
0Instruction address misaligned

Synchronous exception cause code 0.

1Instruction access fault

Synchronous exception cause code 1.

2Illegal instruction

Synchronous exception cause code 2.

3Breakpoint

Synchronous exception cause code 3.

4Load address misaligned

Synchronous exception cause code 4.

5Load access fault

Synchronous exception cause code 5.

6Store/AMO address misaligned

Synchronous exception cause code 6.

7Store/AMO access fault

Synchronous exception cause code 7.

8Environment call from U-mode

Synchronous exception cause code 8.

9Environment call from S-mode

Synchronous exception cause code 9.

12Instruction page fault

Synchronous exception cause code 12.

13Load page fault

Synchronous exception cause code 13.

15Store/AMO page fault

Synchronous exception cause code 15.

18Software check

Synchronous exception cause code 18.

19Hardware error

Synchronous exception cause code 19.

Interrupts
1Supervisor software interrupt

When Interrupt is 1, low cause code 1 indicates a supervisor software interrupt.

5Supervisor timer interrupt

When Interrupt is 1, low cause code 5 indicates a supervisor timer interrupt.

9Supervisor external interrupt

When Interrupt is 1, low cause code 9 indicates a supervisor external interrupt.

13Counter-overflow interrupt

When Interrupt is 1, low cause code 13 indicates a counter-overflow interrupt.

Official Basis & Search Notes

scause splits the S-mode trap cause into the top Interrupt bit and the low Exception Code field. The low field is WLRL, and listed codes must be interpreted in the context selected by the Interrupt bit.

The CSR table lists scause as 0x142, Supervisor, RW.
The Interrupt bit set to 1 indicates an interrupt; cleared to 0 indicates a synchronous exception.
The Exception Code field is WLRL; it must hold values 0-31, and other codes have portable meaning only when specified or implemented.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Supervisor-Level ISA

What To Check First When Reading This CSR

  • - scause is the Supervisor RW CSR at 0x142; insufficient privilege or access to an unimplemented CSR raises an illegal-instruction exception.
  • - Read the Interrupt bit first to distinguish interrupts from synchronous exceptions, then interpret the low cause code using the corresponding table.
  • - The Exception Code field is WLRL; do not treat undefined or platform-unimplemented codes as portable semantics.

Risk Checks Before Writing

  • - Write scause only with cause values supported by the specification or implementation; Exception Code is WLRL, so arbitrary written values are not guaranteed to be retained.
  • - When debugging or constructing software trap context, keep the Interrupt bit and low cause code semantically matched.

Put It Back Into A Real Flow

1

After entering an S-mode trap, read scause.

2

If Interrupt=1, dispatch by supervisor interrupt cause code; if Interrupt=0, dispatch by synchronous exception cause code.

3

Use sepc and stval together with scause to locate the instruction address, memory address, or additional trap information.

FAQ

Can scause be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records scause as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing scause?

The low Exception Code field is WLRL, so arbitrary written codes are not guaranteed to be retained; the Interrupt bit must also match the cause-code context.