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CSR Bit Fields

RISC-V vscause CSR Register

Address 0x242Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vscause holds VS trap cause interrupt flag and code as the VS copy of the corresponding supervisor CSR.

Related Search Terms
vscause CSRvscause 0x242vscause VS copydirect HRW accessguest supervisor state
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63RWException Code62:0RW
Field Map

Understand vscause By Bit Fields

2 key fields
VSXLEN-1

Interrupt

RW

Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

Interrupt (bits VSXLEN-1) — Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

What This Field Controls

  • - Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

Common Values

00

This is a synchronous exception; the low field is interpreted as an exception cause code.

11

This is an interrupt; the low field is interpreted as an interrupt cause code.

↗Open Official Manual
VSXLEN-2:0

Exception Code

RW

VS trap cause code; synchronous exceptions and interrupts are distinguished by the Interrupt bit. ECALL cause codes follow the official Supervisor/Hypervisor trap-cause tables: 9 is S/HS-mode, and 10 is VS-mode. This list does not treat HS trap-specific or G-stage-specific causes as ordinary VS scause-substitute causes.

Exception Code (bits VSXLEN-2:0) — VS trap cause code; synchronous exceptions and interrupts are distinguished by the Interrupt bit. ECALL cause codes follow the official Supervisor/Hypervisor trap-cause tables: 9 is S/HS-mode, and 10 is VS-mode. This list does not treat HS trap-specific or G-stage-specific causes as ordinary VS scause-substitute causes.

What This Field Controls

  • - VS trap cause code; synchronous exceptions and interrupts are distinguished by the Interrupt bit. ECALL cause codes follow the official Supervisor/Hypervisor trap-cause tables: 9 is S/HS-mode, and 10 is VS-mode. This list does not treat HS trap-specific or G-stage-specific causes as ordinary VS scause-substitute causes.

Common Values

Synchronous exceptions
0Instruction address misaligned

Synchronous exception cause code 0.

1Instruction access fault

Synchronous exception cause code 1.

2Illegal instruction

Synchronous exception cause code 2.

3Breakpoint

Synchronous exception cause code 3.

4Load address misaligned

Synchronous exception cause code 4.

5Load access fault

Synchronous exception cause code 5.

6Store/AMO address misaligned

Synchronous exception cause code 6.

7Store/AMO access fault

Synchronous exception cause code 7.

8Environment call from VU-mode

Synchronous exception cause code 8.

9Environment call from S/HS-mode

Synchronous exception cause code 9. With the Hypervisor extension, the official table assigns VS-mode environment calls to cause code 10, so 9 must not be interpreted as a VS-mode ECALL.

10Environment call from VS-mode

Synchronous exception cause code 10; this is the official VS-mode environment-call cause code when the Hypervisor extension is implemented.

12Instruction page fault

Synchronous exception cause code 12.

13Load page fault

Synchronous exception cause code 13.

15Store/AMO page fault

Synchronous exception cause code 15.

18Software check

Synchronous exception cause code 18.

19Hardware error

Synchronous exception cause code 19.

Interrupts
1VS software interrupt

When Interrupt is 1, low cause code 1 indicates a VS software interrupt.

5VS timer interrupt

When Interrupt is 1, low cause code 5 indicates a VS timer interrupt.

9VS external interrupt

When Interrupt is 1, low cause code 9 indicates a VS external interrupt.

13Counter-overflow interrupt

When Interrupt is 1, low cause code 13 indicates a counter-overflow interrupt.

↗Open Official Manual
Official Basis & Search Notes

vscause is a VS supervisor state or trap CSR. The separate CSR address is for M/HS-side management; when V=1, guest access to the corresponding supervisor CSR is substituted with VS state unless an extension specifies otherwise.

vscause address, access class, and width are checked against the official CSR tables: 0x242, HRW, VSXLEN.
The H extension specifies that, when V=1, access to the corresponding supervisor CSR is substituted with the VS CSR.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - vscause's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - Before reading it, confirm that the defining extension such as H, AIA, Sstc, Smstateen, or Smcsrind is implemented.

Risk Checks Before Writing

  • - When writing vscause, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

Update only official fields and do not treat VS state as ordinary HS supervisor state.

FAQ

Can VS-mode directly access vscause's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vscause mainly hold?

vscause holds VS trap cause interrupt flag and code, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.