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CSR Bit Fields

RISC-V vscause CSR Register

Address 0x242Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vscause is the VSXLEN-bit WLRL guest trap-cause register; a trap into VS-mode writes its interrupt flag and translated cause code.

Related Search Terms
vscause CSRvscause 0x242vscause WLRLvscause Interruptvscause cause codeVS trap cause
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63RWException Code62:0RW
Field Map

Understand vscause By Bit Fields

2 key fields
VSXLEN-1

Interrupt

RW

Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

Interrupt (bits VSXLEN-1) — Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

What This Field Controls

  • - Indicates whether the low vscause code denotes an interrupt or a synchronous exception.

Common Values

00

This is a synchronous exception; the low field is interpreted as an exception cause code.

11

This is an interrupt; the low field is interpreted as an interrupt cause code.

↗Open Official Manual
VSXLEN-2:0

Exception Code

RW

WLRL VS trap cause code that must hold the same set of values as scause. VSEI, VSTI, and VSSI traps into VS-mode are written as supervisor cause codes 9, 5, and 1; similar translation of platform interrupts is implementation-dependent. Synchronous VS traps are limited to causes delegated by both medeleg and hedeleg. With AIA, this field must also implement enough bits to represent the largest vstopi.IID value supported by the hart.

Exception Code (bits VSXLEN-2:0) — WLRL VS trap cause code that must hold the same set of values as scause. VSEI, VSTI, and VSSI traps into VS-mode are written as supervisor cause codes 9, 5, and 1; similar translation of platform interrupts is implementation-dependent. Synchronous VS traps are limited to causes delegated by both medeleg and hedeleg. With AIA, this field must also implement enough bits to represent the largest vstopi.IID value supported by the hart.

What This Field Controls

  • - WLRL VS trap cause code that must hold the same set of values as scause. VSEI, VSTI, and VSSI traps into VS-mode are written as supervisor cause codes 9, 5, and 1; similar translation of platform interrupts is implementation-dependent. Synchronous VS traps are limited to causes delegated by both medeleg and hedeleg. With AIA, this field must also implement enough bits to represent the largest vstopi.IID value supported by the hart.

Common Values

Synchronous exceptions
0Instruction address misaligned

Synchronous exception cause code 0.

1Instruction access fault

Synchronous exception cause code 1.

2Illegal instruction

Synchronous exception cause code 2.

3Breakpoint

Synchronous exception cause code 3.

4Load address misaligned

Synchronous exception cause code 4.

5Load access fault

Synchronous exception cause code 5.

6Store/AMO address misaligned

Synchronous exception cause code 6.

7Store/AMO access fault

Synchronous exception cause code 7.

8Environment call from VU-mode

Synchronous exception cause code 8.

12Instruction page fault

Synchronous exception cause code 12.

13Load page fault

Synchronous exception cause code 13.

15Store/AMO page fault

Synchronous exception cause code 15.

18Software check

Synchronous exception cause code 18.

19Hardware error

Synchronous exception cause code 19.

Interrupts
1VS software interrupt

When Interrupt is 1, low cause code 1 indicates a VS software interrupt.

5VS timer interrupt

When Interrupt is 1, low cause code 5 indicates a VS timer interrupt.

9VS external interrupt

When Interrupt is 1, low cause code 9 indicates a VS external interrupt.

13Counter-overflow interrupt

When Interrupt is 1, low cause code 13 indicates a counter-overflow interrupt.

↗Open Official Manual
Official Basis & Search Notes

vscause records the last trap into VS-mode. It substitutes for scause when V=1, and standard VS interrupt causes are translated to guest-visible supervisor cause codes.

vscause address, access class, and width are checked against the official CSR tables: 0x242, HRW, VSXLEN.
The H extension substitutes vscause for scause when V=1; when V=0, vscause does not directly affect machine behavior.
Exception Code is WLRL; VSEI, VSTI, and VSSI traps into VS-mode are translated to cause codes 9, 5, and 1 respectively. AIA also requires enough bits to represent the hart's largest vstopi.IID.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extensionRISC-V Advanced Interrupt Architecture - VS-level interrupt traps

What To Check First When Reading This CSR

  • - vscause's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - The H extension defines vscause; scause accesses substitute to vscause when V=1, and vscause does not directly affect machine behavior when V=0.

Risk Checks Before Writing

  • - Exception Code is WLRL and must support the same value set as scause; software-written values outside supported exception codes are not guaranteed to be retained.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

A trap into VS-mode writes vsepc, vscause, and vstval; interpret the cause code according to the Interrupt bit.

FAQ

Can VS-mode directly access vscause's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vscause mainly hold?

vscause holds the Interrupt flag and cause code for the last trap into VS-mode so the guest trap handler can distinguish and handle an exception or interrupt.