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CSR Bit Fields

RISC-V vsepc CSR Register

Address 0x241Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vsepc is the VSXLEN-bit WARL guest trap return PC; it substitutes for sepc when V=1 and is written on a trap into VS-mode.

Related Search Terms
vsepc CSRvsepc 0x241vsepc WARLvsepc IALIGNvsepc SRETVS trap return address
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
EPC63:0RW
Field Map

Understand vsepc By Bit Fields

1 key fields
VSXLEN-1:0

EPC

RW

WARL guest trap return PC that must hold the same set of values as sepc. Bit 0 is always zero; bits 1:0 are always zero when only IALIGN=32 is supported; with variable IALIGN, reads mask bit 1 to zero while IALIGN=32 although the bit remains writable.

EPC (bits VSXLEN-1:0) — WARL guest trap return PC that must hold the same set of values as sepc. Bit 0 is always zero; bits 1:0 are always zero when only IALIGN=32 is supported; with variable IALIGN, reads mask bit 1 to zero while IALIGN=32 although the bit remains writable.

What This Field Controls

  • - WARL guest trap return PC that must hold the same set of values as sepc. Bit 0 is always zero; bits 1:0 are always zero when only IALIGN=32 is supported; with variable IALIGN, reads mask bit 1 to zero while IALIGN=32 although the bit remains writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

vsepc holds the guest virtual PC on a trap into VS-mode. When V=1, sepc accesses substitute to vsepc, and SRET in VS-mode returns through vsepc.

vsepc address, access class, and width are checked against the official CSR tables: 0x241, HRW, VSXLEN.
The H extension substitutes vsepc for sepc when V=1; when V=0, vsepc does not directly affect machine behavior.
vsepc is WARL, holds the same set of values as sepc, and inherits sepc's IALIGN low-bit rules.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - vsepc's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - The H extension defines vsepc; when V=1, an access to sepc accesses vsepc, while a direct VS-mode access to address 0x241 raises a virtual-instruction exception.

Risk Checks Before Writing

  • - vsepc is WARL; it must hold every valid virtual address but may convert an unrepresentable invalid address to another invalid address it can hold.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

A trap into VS-mode writes vsepc, vscause, and vstval; SRET in VS-mode ultimately sets pc=vsepc.

FAQ

Can VS-mode directly access vsepc's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vsepc mainly hold?

On a trap into VS-mode, it holds the virtual address of the interrupted or faulting instruction; SRET in VS-mode uses it to restore PC.