vsstatus is the H-extension VSXLEN-bit virtual supervisor status CSR; when V=1 it substitutes for sstatus, and when V=0 it normally has no direct machine effect.
VS-mode-visible Dirty summary for FS, VS, or XS; HS-level sstatus.FS does not affect this bit.
SD (bit 63) — VS-mode-visible Dirty summary for FS, VS, or XS; HS-level sstatus.FS does not affect this bit.
No VS-visible FS, VS, or XS field is Dirty.
At least one VS-visible FS, VS, or XS field is Dirty.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bits 62:34) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualControls the effective XLEN for VU-mode; may be implemented as a read-only copy of hstatus.VSXL.
UXL (bits 33:32) — Controls the effective XLEN for VU-mode; may be implemented as a read-only copy of hstatus.VSXL.
VU-mode XLEN is 32.
VU-mode XLEN is 64.
Reserved encoding; portable software should not write or rely on it.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bits 31:25) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualSsdbltrp S-mode-disable-trap field for VS-mode; read-only zero when the relevant extension is not implemented.
SDT (bit 24) — Ssdbltrp S-mode-disable-trap field for VS-mode; read-only zero when the relevant extension is not implemented.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualZicfilp previous ELP state; 0 means no landing pad is expected, and 1 means a landing pad is expected.
SPELP (bit 23) — Zicfilp previous ELP state; 0 means no landing pad is expected, and 1 means a landing pad is expected.
No landing-pad instruction is expected.
A landing-pad instruction is expected.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bits 22:20) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualMakes executable pages readable by explicit loads; vsstatus.MXR affects only the first translation stage (VS-stage).
MXR (bit 19) — Makes executable pages readable by explicit loads; vsstatus.MXR affects only the first translation stage (VS-stage).
Loads read only readable pages; it has no effect when paged virtual memory is inactive.
Loads may read from readable or executable pages.
Controls whether VS-mode loads/stores may access VU pages with U=1; it does not permit VS-mode instruction fetches from user pages.
SUM (bit 18) — Controls whether VS-mode loads/stores may access VU pages with U=1; it does not permit VS-mode instruction fetches from user pages.
VS-mode access to pages with U=1 faults; it has no effect when paged virtual memory is inactive.
VS-mode loads/stores may access U=1 pages, but instruction fetches from user pages remain disallowed.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bit 17) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualRead-only summary of additional user-extension state visible to VS-mode.
XS (bits 16:15) — Read-only summary of additional user-extension state visible to VS-mode.
The associated extension state is off or absent.
The extension state is in its initial state.
The extension state matches the saved context.
The extension state may have been modified.
VS-mode floating-point context status; when V=1, both vsstatus.FS and HS-level sstatus.FS are in effect.
FS (bits 14:13) — VS-mode floating-point context status; when V=1, both vsstatus.FS and HS-level sstatus.FS are in effect.
If either effective FS field is Off, executing a floating-point instruction raises an illegal-instruction exception.
Floating-point state is initial.
Floating-point state matches the saved context.
When V=1, modifying floating-point state sets both vsstatus.FS and HS-level sstatus.FS to Dirty.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bits 12:11) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualVS-mode vector context status; when V=1, vsstatus.VS and the HS-level vector status are both in effect.
VS (bits 10:9) — VS-mode vector context status; when V=1, vsstatus.VS and the HS-level vector status are both in effect.
If either effective VS field is Off, executing a vector instruction or accessing vector CSRs raises an illegal-instruction exception.
Vector state is initial.
Vector state matches the saved context.
When V=1, modifying vector state sets the relevant VS fields to Dirty; implementations may also change Initial/Clean to Dirty at any time.
Nominal privilege before the trap into VS-mode; written by hardware on traps into VS-mode.
SPP (bit 8) — Nominal privilege before the trap into VS-mode; written by hardware on traps into VS-mode.
The nominal previous privilege was U/VU; SRET returns to VU.
The nominal previous privilege was S/VS; SRET returns to VS.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bit 7) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualControls VU-mode explicit memory-access endianness; an implementation may make it a read-only copy of hstatus.VSBE.
UBE (bit 6) — Controls VU-mode explicit memory-access endianness; an implementation may make it a read-only copy of hstatus.VSBE.
VU-mode explicit loads/stores are little-endian.
VU-mode explicit loads/stores are big-endian.
Saved SIE value from before a trap into VS-mode.
SPIE (bit 5) — Saved SIE value from before a trap into VS-mode.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualReserved field; software preserves the value on writes and ignores values read.
WPRI (bits 4:2) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official ManualVS-mode supervisor-level global interrupt enable; delivery also depends on vsie/vsip and delegation state.
SIE (bit 1) — VS-mode supervisor-level global interrupt enable; delivery also depends on vsie/vsip and delegation state.
Supervisor-level interrupts are globally disabled while currently executing in VS-mode.
Supervisor-level interrupts are globally enabled while currently executing in VS-mode.
Reserved field; software preserves the value on writes and ignores values read.
WPRI (bit 0) — Reserved field; software preserves the value on writes and ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
↗Open Official Manualvsstatus is the H-extension VSXLEN-bit copy of sstatus. When V=1, guest access to sstatus is substituted with vsstatus; when V=0, it normally has no direct machine effect except through specific virtual-machine memory-access paths.
HS/M software may directly read or write vsstatus while configuring a guest.
When a guest runs with V=1, hardware uses the vsstatus copy for accesses to sstatus.
On traps into VS-mode, hardware updates vsstatus.SPP, SPIE, SIE, and related VS trap CSRs; SRET returns according to vsstatus state.
No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.
vsstatus holds VS supervisor status state, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.