vsstatus holds VS supervisor status state as the VS copy of the corresponding supervisor CSR.
Summary dirty bit for FS, VS, and XS as visible to VS-mode.
SD (bit 63) — Summary dirty bit for FS, VS, and XS as visible to VS-mode.
No FS, VS, or XS field is Dirty.
At least one of FS, VS, or XS is Dirty.
On RV64, controls the effective XLEN for VU-mode; absent when VSXLEN=32.
UXL (bits 33:32) — On RV64, controls the effective XLEN for VU-mode; absent when VSXLEN=32.
Effective XLEN is 32.
Effective XLEN is 64.
Reserved encoding; portable software must not write or depend on it.
Summary dirty bit for FS, VS, and XS in the RV32 or low-half layout as visible to VS-mode.
SD (bit 31) — Summary dirty bit for FS, VS, and XS in the RV32 or low-half layout as visible to VS-mode.
No FS, VS, or XS field is Dirty.
At least one of FS, VS, or XS is Dirty.
Controls whether executable pages may also be read by loads under VS-stage paging.
MXR (bit 19) — Controls whether executable pages may also be read by loads under VS-stage paging.
Loads read only readable pages; MXR has no effect when paged virtual memory is not active.
Loads may read from readable or executable pages; MXR has no effect when paged virtual memory is not active.
Controls whether VS-mode may access VU pages.
SUM (bit 18) — Controls whether VS-mode may access VU pages.
VS-mode accesses to pages with U=1 fault; SUM has no effect when paged virtual memory is not active.
VS-mode loads/stores may access pages with U=1; VS-mode still cannot execute instructions from user pages.
VS-visible summary of user extension state.
XS (bits 16:15) — VS-visible summary of user extension state.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
VS floating-point state.
FS (bits 14:13) — VS floating-point state.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
VS vector state.
VS (bits 10:9) — VS vector state.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Nominal privilege level before the VS trap.
SPP (bit 8) — Nominal privilege level before the VS trap.
Previous privilege before the VS-mode trap was User; SRET returns to VU-mode.
Previous privilege before the VS-mode trap was Supervisor; SRET returns to VS-mode.
Controls endianness of VU-mode explicit memory accesses; may be a read-only copy of hstatus.VSBE.
UBE (bit 6) — Controls endianness of VU-mode explicit memory accesses; may be a read-only copy of hstatus.VSBE.
VU-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
VU-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
Saved vsstatus.SIE before a VS trap.
SPIE (bit 5) — Saved vsstatus.SIE before a VS trap.
SIE was 0 before the VS-mode trap, or the saved post-return interrupt state is disabled.
SIE was 1 before the VS-mode trap and SRET can restore it under the rules.
Supervisor global interrupt enable for VS-mode.
SIE (bit 1) — Supervisor global interrupt enable for VS-mode.
When currently running in VS-mode, global supervisor interrupts are disabled.
When currently running in VS-mode, global supervisor interrupts are enabled; delivery also depends on vsie/vsip.
vsstatus is a VS supervisor state or trap CSR. The separate CSR address is for M/HS-side management; when V=1, guest access to the corresponding supervisor CSR is substituted with VS state unless an extension specifies otherwise.
M/HS software may access the VS copy through the separate CSR address.
When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.
Update only official fields and do not treat VS state as ordinary HS supervisor state.
No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.
vsstatus holds VS supervisor status state, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.