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CSR Bit Fields

RISC-V vstvec CSR Register

Address 0x205Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vstvec is the VSXLEN-bit virtual supervisor trap-vector CSR; when V=1 it substitutes for stvec, and when V=0 it does not directly affect machine behavior.

Related Search Terms
vstvec CSRvstvec 0x205vstvec BASE MODEVS trap vectorvstvec WARL
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
BASE63:2WARLMODE1:0WARL
Field Map

Understand vstvec By Bit Fields

2 key fields
VSXLEN-1:2

BASE

WARL

VS trap-handler base-address field; the low two address bits are zero when used as an address, and non-Direct modes may require stricter alignment.

BASE (bits VSXLEN-1:2) — VS trap-handler base-address field; the low two address bits are zero when used as an address, and non-Direct modes may require stricter alignment.

What This Field Controls

  • - VS trap-handler base-address field; the low two address bits are zero when used as an address, and non-Direct modes may require stricter alignment.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
1:0

MODE

WARL

VS trap-vector mode field.

MODE (bits 1:0) — VS trap-vector mode field.

What This Field Controls

  • - VS trap-vector mode field.

Common Values

0Direct

Synchronous exceptions and interrupts set pc to BASE.

1Vectored

Synchronous exceptions set pc to BASE; interrupts set pc to BASE + 4 x cause.

>=2Reserved

Reserved encodings; portable software should not write or rely on them.

↗Open Official Manual
Official Basis & Search Notes

vstvec is the VS-mode copy of stvec and stores the guest trap-entry BASE and MODE. It substitutes for stvec when V=1 and has no direct machine effect when V=0.

vstvec address, access class, and width are checked against the local privileged manual: 0x205, HRW, VSXLEN.
BASE and MODE are WARL; MODE=0 is Direct, MODE=1 is Vectored, and other standard encodings are reserved.
When V=1, guest access to stvec is substituted with vstvec; direct access to the separate VS CSR address raises a virtual-instruction exception.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - vstvec is an H-extension VSXLEN-bit HRW CSR and is the VS copy of stvec.
  • - When V=0, vstvec does not directly affect machine behavior.

Risk Checks Before Writing

  • - BASE and MODE are WARL; MODE=0 is Direct, MODE=1 is Vectored, and other standard encodings are reserved.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

Update only official fields and do not treat VS state as ordinary HS supervisor state.

FAQ

Can VS-mode directly access vstvec's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vstvec mainly hold?

vstvec holds the VS trap-vector base and mode used to select the VS trap entry point when V=1.