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CSR Bit Fields

RISC-V vstvec CSR Register

Address 0x205Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vstvec holds VS trap-vector base and mode as the VS copy of the corresponding supervisor CSR.

Related Search Terms
vstvec CSRvstvec 0x205vstvec VS copyVS CSR direct accessguest supervisor state
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
BASE63:2RWMODE1:0RW
Field Map

Understand vstvec By Bit Fields

2 key fields
VSXLEN-1:2

BASE

RW

VS trap-vector base-address field.

BASE (bits VSXLEN-1:2) — VS trap-vector base-address field.

What This Field Controls

  • - VS trap-vector base-address field.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
1:0

MODE

RW

VS trap-vector mode field.

MODE (bits 1:0) — VS trap-vector mode field.

What This Field Controls

  • - VS trap-vector mode field.

Common Values

0Direct

All synchronous exceptions and interrupts set pc to BASE.

1Vectored

Synchronous exceptions set pc to BASE; interrupts set pc to BASE + 4 x cause.

>=2Reserved

Reserved encoding; portable software must not write or depend on it.

↗Open Official Manual
Official Basis & Search Notes

vstvec is a VS supervisor state or trap CSR. The separate CSR address is for M/HS-side management; when V=1, guest access to the corresponding supervisor CSR is substituted with VS state unless an extension specifies otherwise.

vstvec address, access class, and width are checked against the official CSR tables: 0x205, HRW, VSXLEN.
The H extension specifies that, when V=1, access to the corresponding supervisor CSR is substituted with the VS CSR.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - vstvec's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - Before reading it, confirm that the defining extension such as H, AIA, Sstc, Smstateen, or Smcsrind is implemented.

Risk Checks Before Writing

  • - When writing vstvec, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

Update only official fields and do not treat VS state as ordinary HS supervisor state.

FAQ

Can VS-mode directly access vstvec's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vstvec mainly hold?

vstvec holds VS trap-vector base and mode, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.