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CSR Bit Fields

RISC-V vsie CSR Register

Address 0x204Privilege Hypervisor direct / VS aliasAccess HRW / VSXLEN; 64-bit with AIAHypervisor and virtualization CSRs

vsie is the VS-mode supervisor interrupt-enable CSR; when V=1 it substitutes for sie, standard bits are aliases or read-only zero according to hideleg delegation, and AIA can widen it to 64 bits.

Related Search Terms
vsie CSRvsie 0x204vsie SSIE STIEvsie hidelegvsie AIAvsieh high half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Platform/custom interrupt enables63:16WARL/RO0Reserved0RO0
Field Map

Understand vsie By Bit Fields

10 key fields
VSXLEN-1:16

Platform/custom interrupt enables

WARL/RO0

VS interrupt-enable bits outside the standard low 16 bits; only platform- or extension-defined bits whose interrupts can become pending are writable, otherwise they are read-only zero or reserved.

Platform/custom interrupt enables (bits VSXLEN-1:16) — VS interrupt-enable bits outside the standard low 16 bits; only platform- or extension-defined bits whose interrupts can become pending are writable, otherwise they are read-only zero or reserved.

What This Field Controls

  • - VS interrupt-enable bits outside the standard low 16 bits; only platform- or extension-defined bits whose interrupts can become pending are writable, otherwise they are read-only zero or reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:14

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 15:14) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
13

LCOFIE

Alias/RO0

Alias of sie.LCOFIE when Shlcofideleg is implemented and hideleg[13]=1; otherwise read-only zero.

LCOFIE (bit 13) — Alias of sie.LCOFIE when Shlcofideleg is implemented and hideleg[13]=1; otherwise read-only zero.

What This Field Controls

  • - Alias of sie.LCOFIE when Shlcofideleg is implemented and hideleg[13]=1; otherwise read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:10

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 12:10) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
9

SEIE

Alias/RO0

Alias of hie.VSEIE when hideleg[10]=1; otherwise read-only zero.

SEIE (bit 9) — Alias of hie.VSEIE when hideleg[10]=1; otherwise read-only zero.

What This Field Controls

  • - Alias of hie.VSEIE when hideleg[10]=1; otherwise read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
8:6

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 8:6) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
5

STIE

Alias/RO0

Alias of hie.VSTIE when hideleg[6]=1; otherwise read-only zero.

STIE (bit 5) — Alias of hie.VSTIE when hideleg[6]=1; otherwise read-only zero.

What This Field Controls

  • - Alias of hie.VSTIE when hideleg[6]=1; otherwise read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:2

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 4:2) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
1

SSIE

Alias/RO0

Alias of hie.VSSIE when hideleg[2]=1; otherwise read-only zero.

SSIE (bit 1) — Alias of hie.VSSIE when hideleg[2]=1; otherwise read-only zero.

What This Field Controls

  • - Alias of hie.VSSIE when hideleg[2]=1; otherwise read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
0

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bit 0) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

vsie is the VS supervisor interrupt-enable CSR. When V=1, guest access to sie is substituted with vsie; standard low bits become aliases or read-only zero according to hideleg, and AIA can widen this state to 64 bits.

vsie address and access class are checked against the local privileged CSR table: 0x204, HRW; the local H-extension text defines it as VSXLEN-bit, while the AIA specification can widen it to 64 bits.
Standard bits LCOFIE, SEIE, STIE, and SSIE are aliases only when the corresponding hideleg bit delegates them; otherwise they are read-only zero.
On RV32, AIA high-half interrupt-enable bits are accessed through vsieh; write only officially defined and writable bits.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extensionRISC-V Advanced Interrupt Architecture CSR chapter

What To Check First When Reading This CSR

  • - vsie is an H-extension VSXLEN-bit HRW CSR; AIA widens it to 64 bits.
  • - When V=1, guest access to sie is substituted with vsie; direct access to the separate VS CSR address raises a virtual-instruction exception.

Risk Checks Before Writing

  • - Standard bits 13, 9, 5, and 1 are aliases only when the corresponding hideleg bit delegates them; otherwise they are read-only zero.
  • - Undefined, reserved, or non-pending interrupt bits must not be treated as fixed 1=enabled bits; RV32 accesses the upper 32 bits through vsieh.

Put It Back Into A Real Flow

1

First confirm whether the VS interrupt is delegated to VS-mode through hideleg.

2

Set the corresponding enable bit in vsie while also checking the vsip pending bit and vsstatus.SIE.

3

AIA/RV32 high-half interrupt bits are accessed through vsieh and are controlled by AIA state-enable bits.

FAQ

Are vsie standard interrupt-enable bits always writable?

No. LCOFIE, SEIE, STIE, and SSIE are effective aliases only when the corresponding hideleg bit is 1; otherwise they are read-only zero.

How does RV32 access the AIA-widened upper half of vsie?

AIA defines vsieh as the 32-bit high-half CSR for vsie[63:32]; those upper bits may all be merely read-only zero.