RISC-V sepc CSR Register

Address 0x141Privilege SupervisorAccess RW / SXLENSupervisor status, trap, and interrupt CSRs

Supervisor exception program counter; holds the virtual address captured on entry to an S-mode trap.

Related Search Terms

sepc CSR sepc 0x141 supervisor exception PC SRET return address sepc IALIGN RISC-V sepc

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0WARL

Field Map

Understand sepc By Bit Fields

1 key fields

SXLEN-1:0

VALUE

WARL

S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

VALUE (bits SXLEN-1:0) — S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

What This Field Controls

- S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

sepc holds the S-mode trap-return address. It is not an ordinary integer register: the address field is WARL, bit 0 is fixed zero, and IALIGN=32 masks bit 1 on reads.

The CSR table lists sepc as 0x141, Supervisor, RW.

sepc must hold all valid virtual addresses and may hold some invalid addresses; writes of other invalid addresses are constrained by WARL behavior.

Bit 0 is always zero; when IALIGN=32, bit 1 reads as zero while the underlying writable value is retained.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Supervisor-Level ISA

What To Check First When Reading This CSR

- sepc is the Supervisor RW CSR at 0x141; insufficient privilege or access to an unimplemented CSR raises an illegal-instruction exception.
- Reading sepc returns the S-mode trap-return address; when IALIGN=32, bit 1 of the read value is masked to zero.
- sepc is WARL, so software should use the read-back value to confirm the address representation accepted by the implementation.

Risk Checks Before Writing

- When writing sepc, rely only on the specified WARL behavior; an implementation may convert an invalid address into another invalid address it can represent.
- Do not treat bit 0 as state; it is always zero. When IALIGN=32, bit 1 remains writable but is masked on reads.

Put It Back Into A Real Flow

After entering an S-mode trap, read sepc to obtain the virtual address needed for return or diagnosis.

If the handler needs to skip or retry an instruction, write the new sepc value subject to WARL behavior.

Before SRET, confirm sepc and return-state fields such as sstatus.SPP/SPIE are consistent.

FAQ

Can sepc be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sepc as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing sepc?

sepc is WARL. A written address is not guaranteed to be retained as an ordinary integer; bit 0 is fixed zero, and IALIGN=32 masks bit 1 on reads.