RISC-V sepc CSR Register

Address 0x141Privilege SupervisorAccess RW / SXLENSupervisor status, trap, and interrupt CSRs

Supervisor exception program counter; holds the virtual address captured on entry to an S-mode trap.

Related Search Terms

sepc CSR sepc 0x141 supervisor exception PC SRET return address sepc IALIGN RISC-V sepc

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0WARL

Field Map

Understand sepc By Bit Fields

1 key fields

SXLEN-1:0

VALUE

WARL

S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero. Implementations supporting only IALIGN=32 have both low bits fixed zero; implementations allowing IALIGN to vary between 16 and 32 mask bit 1 on reads (including SRET) when IALIGN=32, while keeping it writable.

VALUE (bits SXLEN-1:0) — S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero. Implementations supporting only IALIGN=32 have both low bits fixed zero; implementations allowing IALIGN to vary between 16 and 32 mask bit 1 on reads (including SRET) when IALIGN=32, while keeping it writable.

What This Field Controls

- S-mode trap-return virtual address. sepc is WARL and must hold all valid virtual addresses; bit 0 is always zero. Implementations supporting only IALIGN=32 have both low bits fixed zero; implementations allowing IALIGN to vary between 16 and 32 mask bit 1 on reads (including SRET) when IALIGN=32, while keeping it writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

sepc holds the S-mode trap-return address. The address field is WARL and bit 0 is fixed zero; fixed IALIGN=32 keeps both low bits zero, while variable IALIGN=16/32 supports conditional read masking of bit 1.

The CSR table lists sepc as 0x141, Supervisor, RW.

sepc must hold all valid virtual addresses and may hold some invalid addresses; writes of other invalid addresses are constrained by WARL behavior.

Bit 0 is always zero; fixed IALIGN=32 keeps both low bits zero. If the implementation allows IALIGN to vary between 16 and 32, bit 1 reads as zero (including SRET) when IALIGN=32 but remains writable.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Supervisor-Level ISA

What To Check First When Reading This CSR

- sepc has Supervisor as its lowest access level. Instructions accessing nonexistent CSRs are reserved and do not qualify for the following virtual-instruction exception. Insufficient privilege to access an implemented CSR normally raises illegal instruction; with H, VU access to an implemented supervisor CSR raises virtual instruction when the same read/write would be allowed in HS-mode, assuming mstatus.TVM=0.
- Reading sepc returns the S-mode trap-return address. Fixed IALIGN=32 keeps both low bits zero; when IALIGN can vary between 16 and 32, IALIGN=32 masks bit 1 on reads, including SRET.
- sepc is WARL, so software should use the read-back value to confirm the address representation accepted by the implementation.

Risk Checks Before Writing

- When writing sepc, rely only on the specified WARL behavior; an implementation may convert an invalid address into another invalid address it can represent.
- Bit 0 is always zero. With fixed IALIGN=32 both low bits are zero; only implementations allowing IALIGN to vary between 16 and 32 keep bit 1 writable while masking it on reads when IALIGN=32.

Put It Back Into A Real Flow

After entering an S-mode trap, read sepc to obtain the virtual address needed for return or diagnosis.

If the handler needs to skip or retry an instruction, write the new sepc value subject to WARL behavior.

Before SRET, confirm sepc and return-state fields such as sstatus.SPP/SPIE are consistent.

FAQ

Can sepc be accessed from any privilege level?

sepc has Supervisor as its lowest access level. Instructions accessing nonexistent CSRs are reserved and do not qualify for the following virtual-instruction exception. Insufficient privilege to access an implemented CSR normally raises illegal instruction; with H, VU access to an implemented supervisor CSR raises virtual instruction when the same read/write would be allowed in HS-mode, assuming mstatus.TVM=0.

What is easiest to miss when writing sepc?

sepc is WARL, so a written address need not be retained unchanged. Bit 0 is always zero; fixed IALIGN=32 keeps both low bits zero. Only implementations allowing IALIGN to vary between 16 and 32 keep bit 1 writable while masking it on reads (including SRET) when IALIGN=32.