RISC-V sepc CSR Register

Address 0x141Privilege SupervisorAccess RW / XLENSupervisor status, trap, and interrupt CSRs

Supervisor exception program counter; holds the address of the instruction that triggered an S-mode trap.

Related Search Terms

sepc CSR sepc 0x141 supervisor exception PC SRET return address sepc IALIGN RISC-V sepc

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RW

Field Map

Understand sepc By Bit Fields

1 key fields

XLEN-1:0

VALUE

S-mode exception return PC. Bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

VALUE (bits XLEN-1:0) — S-mode exception return PC. Bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

What This Field Controls

- S-mode exception return PC. Bit 0 is always zero; when IALIGN=32, bit 1 is masked to zero on reads while remaining writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

sepc is a RW CSR in supervisor status, trap, and interrupt csrs at 0x141. Check privilege and implemented extensions before interpreting its bit fields.

sepc address, lowest access privilege, and access class are checked against the official CSR table: 0x141, Supervisor, RW.

Read it as part of supervisor status, trap, and interrupt csrs before interpreting the bit-field table on this page.

Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements sepc; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0x141 and the lowest access privilege (Supervisor) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads sepc to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can sepc be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sepc as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing sepc?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.