RISC-V mepc CSR Register

Address 0x341Privilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine exception program counter; holds the virtual address of the instruction interrupted or encountering an exception when a trap enters M-mode.

Related Search Terms

mepc CSR mepc 0x341 machine exception PC MRET return address mepc IALIGN RISC-V mepc

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

EPC63:0WARL

Field Map

Understand mepc By Bit Fields

1 key fields

MXLEN-1:0

EPC

WARL

M-mode exception return PC. mepc[0] is always zero; on implementations supporting only IALIGN=32, mepc[1:0] are always zero. If IALIGN can vary between 16 and 32, mepc[1] is masked to zero on reads when IALIGN=32 but remains writable.

EPC (bits MXLEN-1:0) — M-mode exception return PC. mepc[0] is always zero; on implementations supporting only IALIGN=32, mepc[1:0] are always zero. If IALIGN can vary between 16 and 32, mepc[1] is masked to zero on reads when IALIGN=32 but remains writable.

What This Field Controls

- M-mode exception return PC. mepc[0] is always zero; on implementations supporting only IALIGN=32, mepc[1:0] are always zero. If IALIGN can vary between 16 and 32, mepc[1] is masked to zero on reads when IALIGN=32 but remains writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mepc is the MXLEN-bit Machine-mode exception PC CSR at 0x341. On entry to an M-mode trap, it is written with the relevant instruction virtual address; MRET resumes the PC from it. Low bits are constrained by IALIGN, and the field is WARL.

The official CSR table lists mepc at 0x341 with Machine-mode read/write access.

mepc[0] is always zero; with only IALIGN=32, mepc[1:0] are always zero; with dynamic IALIGN=32, mepc[1] is masked on reads but remains writable.

mepc is WARL and must hold all valid virtual addresses, but need not hold all possible invalid addresses.

RISC-V Privileged Architecture Manual v20260120 RISC-V Privileged Architecture Manual v20260120, Machine-Level ISA

What To Check First When Reading This CSR

- mepc is an MXLEN-bit Machine-mode read/write CSR at 0x341, with WARL field behavior.
- When a trap is taken into M-mode, hardware writes the virtual address of the interrupted instruction or the instruction that encountered the exception to mepc.
- The implicit read by MRET is also subject to the mepc[1] read masking rule when IALIGN=32.

Risk Checks Before Writing

- mepc must be able to hold all valid virtual addresses; an implementation may convert an invalid address into another invalid address that mepc can hold before writing it.
- When writing low bits, account for IALIGN: mepc[0] is always zero, and mepc[1] appears as zero on reads when IALIGN=32.

Put It Back Into A Real Flow

The trap handler reads mepc to identify the instruction address before the trap entered M-mode.

If software needs to skip or retry an instruction, it writes the new mepc according to IALIGN and WARL rules.

On MRET, the processor resumes execution from the address specified by mepc.

FAQ

Can mepc be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR table gives the lowest access privilege; mepc is at 0x341 with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mepc?

The common pitfall is ignoring low-bit and WARL rules. mepc[0] is always zero; when IALIGN=32, mepc[1] appears as zero on reads; invalid addresses may be converted by the implementation into another invalid address it can hold.