RISC-V stval CSR Register

Address 0x143Privilege SupervisorAccess RW / SXLENSupervisor status, trap, and interrupt CSRs

Supervisor trap value register; holds exception-specific information for an S-mode trap, or zero when no information is provided.

Related Search Terms

stval CSR stval 0x143 supervisor trap value stval fault address stval illegal instruction RISC-V stval

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0WARL

Field Map

Understand stval By Bit Fields

1 key fields

SXLEN-1:0

VALUE

WARL

Exception-specific value. stval is WARL and must hold all valid virtual addresses plus zero; if faulting instruction bits are returned, it must also hold all values less than 2^N, where N is the smaller of SXLEN and ILEN.

VALUE (bits SXLEN-1:0) — Exception-specific value. stval is WARL and must hold all valid virtual addresses plus zero; if faulting instruction bits are returned, it must also hold all values less than 2^N, where N is the smaller of SXLEN and ILEN.

What This Field Controls

- Exception-specific value. stval is WARL and must hold all valid virtual addresses plus zero; if faulting instruction bits are returned, it must also hold all values less than 2^N, where N is the smaller of SXLEN and ILEN.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

stval is an exception-information register, not meaningful for every trap. It is WARL; zero may mean no information was provided or may be a valid value for the exception.

The CSR table lists stval as 0x143, Supervisor, RW.

Breakpoint, address-misaligned, access-fault, page-fault, and hardware-error exceptions may write the faulting virtual address; illegal-instruction exceptions may write instruction bits; software-check exceptions write a cause encoding; other traps write zero.

stval is WARL; it must hold all valid virtual addresses plus zero, and if illegal-instruction bits are returned it must also hold the corresponding instruction-bit values.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Supervisor-Level ISA

What To Check First When Reading This CSR

- stval is the Supervisor RW CSR at 0x143; insufficient privilege or access to an unimplemented CSR raises an illegal-instruction exception.
- Interpret stval only for exception types that define additional information; other traps without defined stval information write zero.
- Illegal-instruction exceptions may write the shortest informative instruction bits, or may write zero; do not assume all implementations provide instruction bits.

Risk Checks Before Writing

- stval is WARL; non-address or invalid-address writes are not guaranteed to be retained unchanged.
- Writing stval does not by itself fix the exception cause; trap handling should still be based on scause and the relevant translation or access rules.

Put It Back Into A Real Flow

After entering an S-mode trap, read scause first to identify the exception type.

If that exception type defines stval information, read stval as additional information such as a virtual address or illegal-instruction bits.

If stval is zero, do not rule out the exception from that value alone; zero may be a valid value or may mean the implementation provided no information.

FAQ

Can stval be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records stval as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

Does stval equal to zero always mean there is no fault address?

No. The specification allows zero for some exceptions, and zero can also be a valid value. Interpret stval together with the exception type in scause.