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CSR Bit Fields

RISC-V vstval CSR Register

Address 0x243Privilege Hypervisor direct / VS aliasAccess HRW / VSXLENHypervisor and virtualization CSRs

vstval is the VSXLEN-bit WARL guest trap-value register; a trap into VS-mode writes it according to stval's exception-specific rules.

Related Search Terms
vstval CSRvstval 0x243vstval WARLvstval fault addressvstval instruction bitsVS trap value
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
TVAL63:0RW
Field Map

Understand vstval By Bit Fields

1 key fields
VSXLEN-1:0

TVAL

RW

WARL VS trap value that must hold the same set of values as stval, including every valid virtual address and zero; if faulting-instruction reporting is implemented, it must also hold the required low-value range.

TVAL (bits VSXLEN-1:0) — WARL VS trap value that must hold the same set of values as stval, including every valid virtual address and zero; if faulting-instruction reporting is implemented, it must also hold the required low-value range.

What This Field Controls

  • - WARL VS trap value that must hold the same set of values as stval, including every valid virtual address and zero; if faulting-instruction reporting is implemented, it must also hold the required low-value range.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

vstval provides exception-specific auxiliary data for a trap into VS-mode. It inherits stval's valid-address, optional instruction-bit, software-check, and zero-value rules.

vstval address, access class, and width are checked against the official CSR tables: 0x243, HRW, VSXLEN.
The H extension substitutes vstval for stval when V=1; when V=0, vstval does not directly affect machine behavior.
vstval is WARL and must hold the same value set as stval; the value written on a trap depends on the exception type and platform rules.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - vstval's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - The H extension defines vstval; stval accesses substitute to vstval when V=1, and vstval does not directly affect machine behavior when V=0.

Risk Checks Before Writing

  • - vstval is WARL; an implementation may convert an unrepresentable invalid address to another invalid address it can hold, so arbitrary written values need not be preserved exactly.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

A trap into VS-mode writes vsepc, vscause, and vstval; read vscause first and interpret vstval under the matching exception rule.

FAQ

Can VS-mode directly access vstval's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vstval mainly hold?

According to the exception identified by vscause, it holds a faulting virtual address, optional instruction bits, a software-check cause, or zero.