RISC-V mtinst CSR Register

Address 0x34APrivilege MachineAccess RW / XLENMachine status, trap, and interrupt CSRs

Machine trap instruction transformed register (H extension only); holds the transformed trap instruction.

Related Search Terms

mtinst CSR mtinst 0x34A machine trap instruction transformed instruction H extension trap RISC-V mtinst

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RW

Field Map

Understand mtinst By Bit Fields

1 key fields

XLEN-1:0

VALUE

Full register value of mtinst; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

VALUE (bits XLEN-1:0) — Full register value of mtinst; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

What This Field Controls

- Full register value of mtinst; bits not split out here follow the relevant extension or privileged specification, and reserved or WPRI fields should be preserved when writing other fields and ignored on reads.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtinst is a RW CSR in machine status, trap, and interrupt csrs at 0x34A. Check privilege and implemented extensions before interpreting its bit fields.

mtinst address, lowest access privilege, and access class are checked against the official CSR table: 0x34A, Machine, RW.

Read it as part of machine status, trap, and interrupt csrs before interpreting the bit-field table on this page.

Modify only target fields and preserve unchanged bits; interpret WPRI and reserved fields only as the official specification and implementation define them.

RISC-V Privileged Architecture Manual RISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

- First confirm that the current hart implements mtinst; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
- Use address 0x34A and the lowest access privilege (Machine) to decide whether software may read it directly.
- Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads mtinst to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can mtinst be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mtinst as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtinst?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.