RISC-V mtinst CSR Register

Address 0x34APrivilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine trap-instruction CSR added by the Hypervisor extension; on traps into M-mode it is written with zero, a transformed trapping instruction, a custom value only for a non-standard trapping instruction, or a special pseudoinstruction.

Related Search Terms

mtinst CSR mtinst 0x34A machine trap instruction mtinst transformed instruction H extension trap RISC-V mtinst

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

VALUE63:0RW

Field Map

Understand mtinst By Bit Fields

1 key fields

MXLEN-1:0

VALUE

Complete mtinst value. This CSR is WARL and need only hold values the implementation may automatically write on a trap; a nonzero value must be a permitted transformed instruction, a custom value used only for a non-standard trapping instruction, or a special pseudoinstruction.

VALUE (bits MXLEN-1:0) — Complete mtinst value. This CSR is WARL and need only hold values the implementation may automatically write on a trap; a nonzero value must be a permitted transformed instruction, a custom value used only for a non-standard trapping instruction, or a special pseudoinstruction.

What This Field Controls

- Complete mtinst value. This CSR is WARL and need only hold values the implementation may automatically write on a trap; a nonzero value must be a permitted transformed instruction, a custom value used only for a non-standard trapping instruction, or a special pseudoinstruction.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtinst is an MXLEN-bit Machine-mode read/write CSR at 0x34A added by the Hypervisor extension. On traps into M-mode it holds zero or an officially defined trap-instruction helper value; the CSR is WARL.

The official CSR table lists mtinst at 0x34A, MRW, described as Machine trap instruction (transformed).

The Hypervisor extension adds mtval2 and mtinst.

mtinst is WARL and need only hold trap values the implementation may automatically write; software must validate a nonzero value's legal class before interpreting it.

RISC-V Privileged Architecture Manual v20260120, CSR table RISC-V Privileged Architecture Manual v20260120, Hypervisor extension

What To Check First When Reading This CSR

- mtinst is added by the Hypervisor extension.
- Interrupts always write zero to mtinst; a nonzero synchronous-exception value must be one of the officially permitted value classes.
- Software may treat an unrecognized mtinst value as zero; it must fully validate an encoding before interpreting a nonzero value.

Risk Checks Before Writing

- mtinst is WARL; a software write of an unsupported value may be normalized by the implementation to another legal value.
- Do not rely on mtinst to hold arbitrary instruction encodings; it need only hold values the implementation may automatically write on traps.

Put It Back Into A Real Flow

After a trap enters M-mode, software first uses mcause to identify whether the trap is an interrupt or a synchronous exception.

If mtinst is nonzero, validate its encoding against the official legal value classes instead of treating it directly as a raw instruction word.

For guest-page faults, combine mtval, mtval2, and mtinst to identify the faulting virtual address, guest physical address, and whether an implicit VS-stage access was involved.

FAQ

Can mtinst be accessed from any privilege level?

No. The official CSR table lists mtinst as an MRW CSR at 0x34A, with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtinst?

The common mistake is treating mtinst as a raw instruction copy. The official rules allow zero, transformed instructions, custom values only for non-standard trapping instructions, or special pseudoinstructions; an unrecognized value may be treated as zero.