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CSR Bit Fields

RISC-V htinst CSR Register

Address 0x64APrivilege Hypervisor (H extension)Access HRW / HSXLENHypervisor and virtualization CSRs

htinst holds optional transformed-instruction or pseudoinstruction information when a trap enters HS mode.

Related Search Terms
htinst CSRhtinst 0x64AHypervisor trap instructionhtinst WARL
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
HTINST63:0WARL
Field Map

Understand htinst By Bit Fields

1 key fields
HSXLEN-1:0

HTINST

WARL

On a trap into HS mode, hardware may write a nonzero transformed standard instruction, custom value, or specified pseudoinstruction; interrupts write zero. An implementation need only hold values it may write automatically.

HTINST (bits HSXLEN-1:0) — On a trap into HS mode, hardware may write a nonzero transformed standard instruction, custom value, or specified pseudoinstruction; interrupts write zero. An implementation need only hold values it may write automatically.

What This Field Controls

  • - On a trap into HS mode, hardware may write a nonzero transformed standard instruction, custom value, or specified pseudoinstruction; interrupts write zero. An implementation need only hold values it may write automatically.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

htinst is not an unconditional copy of the original instruction; an implementation may substitute zero for a transformation at any time.

Figure 63 defines the whole-register format; Section 15.6.3 defines permitted trap-written values.
Software must validate a complete nonzero encoding for forward compatibility.
RISC-V Privileged Architecture Manual - Hypervisor trap instruction

What To Check First When Reading This CSR

  • - A nonzero value must be fully validated against the allowed categories; an unrecognized value can safely be treated as zero.
  • - Automatically written values for synchronous exceptions are limited by Table 55; implicit VS-stage accesses on guest-page faults use Table 56 pseudoinstructions under the stated conditions.

Risk Checks Before Writing

  • - htinst is WARL; software should read back after writing to confirm the stored value.

Put It Back Into A Real Flow

1

Interpret htinst only while handling a trap into HS mode.

2

First distinguish zero, interrupt, transformed standard instruction, custom value, and specified pseudoinstruction; do not infer full meaning from only low bits.