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CSR Bit Fields

RISC-V mtval2 CSR Register

Address 0x34BPrivilege MachineAccess RW / MXLENMachine status, trap, and interrupt CSRs

Machine second trap-value CSR added by the Hypervisor extension; on guest-page faults into M-mode it holds the guest physical address shifted right by two bits or zero.

Related Search Terms
mtval2 CSRmtval2 0x34Bsecond trap valuemtval2 GPAtwo stage translationRISC-V mtval2
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RW
Field Map

Understand mtval2 By Bit Fields

1 key fields
MXLEN-1:0

VALUE

RW

Complete mtval2 value. On guest-page faults, this value may be the guest physical address shifted right by two bits; it is zero when no information is provided. The CSR is WARL, must hold zero, and need only represent an arbitrary subset of other GPA>>2 values.

VALUE (bits MXLEN-1:0) — Complete mtval2 value. On guest-page faults, this value may be the guest physical address shifted right by two bits; it is zero when no information is provided. The CSR is WARL, must hold zero, and need only represent an arbitrary subset of other GPA>>2 values.

What This Field Controls

  • - Complete mtval2 value. On guest-page faults, this value may be the guest physical address shifted right by two bits; it is zero when no information is provided. The CSR is WARL, must hold zero, and need only represent an arbitrary subset of other GPA>>2 values.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mtval2 is an MXLEN-bit Machine-mode read/write CSR at 0x34B added by the Hypervisor extension. On guest-page faults into M-mode it holds GPA>>2 or zero; the CSR is WARL and, apart from zero, need only support an arbitrary subset.

The official CSR table lists mtval2 at 0x34B, MRW, described as Machine second trap value.
The Hypervisor extension adds mtval2 and mtinst; Ssdbltrp also requires mtval2.
mtval2 is WARL and must hold zero; apart from zero it need only represent an arbitrary subset of GPA>>2 values, and this page does not describe it as the complete GPA.
RISC-V Privileged Architecture Manual v20260120, CSR tableRISC-V Privileged Architecture Manual v20260120, Hypervisor extension

What To Check First When Reading This CSR

  • - mtval2 is added by the Hypervisor extension; the Ssdbltrp extension also requires this CSR.
  • - When a guest-page fault enters M-mode, mtval2 holds the guest physical address shifted right by two bits or zero; other traps normally write zero, but an Ssdbltrp double trap writes to mtval2 the value that would otherwise have been written to mcause, and a future standard or extension may define other uses.
  • - Interpret mtval2 together with mcause, mtval, and mtinst to identify the trap type, original virtual address, and whether an implicit VS-stage access was involved.

Risk Checks Before Writing

  • - mtval2 is WARL; outside zero, the implementation need only represent an arbitrary subset of GPA>>2 values, and other writes may be normalized.
  • - Do not treat mtval2 as the full guest physical address; the official format omits the low two bits.

Put It Back Into A Real Flow

1

After a guest-page fault enters M-mode, software first uses mcause to confirm the trap cause.

2

Read mtval for the faulting virtual address and mtval2 for GPA>>2 when the implementation provides it.

3

If mtinst is nonzero, use its legal value to determine whether an implicit memory access for VS-stage translation was involved.

FAQ

Can mtval2 be accessed from any privilege level?

No. The official CSR table lists mtval2 as an MRW CSR at 0x34B, with Machine as the lowest access level. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing mtval2?

The easy mistake is forgetting that the low two bits are not held in mtval2. mtval2 stores the guest physical address shifted right by two bits, not the full GPA.