Supervisor status register; a restricted view of mstatus containing S-mode-relevant fields.
The sstatus (Supervisor Status) CSR at address 0x100 is a restricted S-mode view of mstatus. It provides SIE (bit 1) for S-mode interrupt enable, SPIE (bit 5) to save pre-trap interrupt state, and SPP (bit 8) to record the privilege level before a trap. Additional fields include SUM (bit 18) for permitting supervisor access to user memory and MXR (bit 19) for making executable pages readable. S-mode interrupt delivery is controlled by S-mode privilege state plus sip/sie pending and enable bits.
State-dirty summary bit; set when FS, VS, or XS is Dirty. In RV32 this appears at bit 31.
SD (bit 63) — State-dirty summary bit; set when FS, VS, or XS is Dirty. In RV32 this appears at bit 31.
No FS, VS, or XS field is Dirty.
At least one of FS, VS, or XS is Dirty.
Effective XLEN encoding for U-mode on RV64; this field does not exist when SXLEN=32.
UXL (bits 33:32) — Effective XLEN encoding for U-mode on RV64; this field does not exist when SXLEN=32.
Effective XLEN is 32.
Effective XLEN is 64.
Reserved encoding; portable software must not write or depend on it.
S-mode-disable-trap bit introduced by Ssdbltrp; explicitly writing 1 clears SIE, and SRET clears SDT. It is read-only zero when Ssdbltrp is not implemented.
SDT (bit 24) — S-mode-disable-trap bit introduced by Ssdbltrp; explicitly writing 1 clears SIE, and SRET clears SDT. It is read-only zero when Ssdbltrp is not implemented.
When Ssdbltrp is implemented and enabled, if SDT is 0 before a trap is taken into S-mode, hardware sets it to 1 and delivers the trap as expected.
When Ssdbltrp is implemented and enabled, if SDT is already 1 when a trap is to be taken into S-mode, the trap is an unexpected trap and a double-trap exception is delivered to M-mode as specified.
Previous expected landing pad state added by Zicfilp; accesses mstatus.SPELP when V=0 and vsstatus.SPELP when V=1.
SPELP (bit 23) — Previous expected landing pad state added by Zicfilp; accesses mstatus.SPELP when V=0 and vsstatus.SPELP when V=1.
No landing-pad instruction is expected.
A landing-pad instruction is expected.
Allows loads from executable pages.
MXR (bit 19) — Allows loads from executable pages.
Loads read only readable pages; MXR has no effect when paged virtual memory is not active.
Loads may read from readable or executable pages; MXR has no effect when paged virtual memory is not active.
Allows S-mode to access U-mode pages; SUM is read-only zero if satp.MODE is read-only zero.
SUM (bit 18) — Allows S-mode to access U-mode pages; SUM is read-only zero if satp.MODE is read-only zero.
S-mode accesses to pages with U=1 fault; SUM has no effect when paged virtual memory is not active.
S-mode loads/stores may access pages with U=1; S-mode still cannot execute instructions from user pages.
Summary of additional user-extension state; read-only zero when no additional user extensions require new state.
XS (bits 16:15) — Summary of additional user-extension state; read-only zero when no additional user extensions require new state.
All additional user-extension state is Off.
No additional extension state is Clean or Dirty, and at least one is Initial.
No additional extension state is Dirty, and at least one is Clean.
At least one additional extension state is Dirty.
Floating-point state. It must not be read-only zero when F is implemented; with S-mode but no F, it may optionally be read-only zero, allowing or disallowing F emulation through invisible traps to M-mode.
FS (bits 14:13) — Floating-point state. It must not be read-only zero when F is implemented; with S-mode but no F, it may optionally be read-only zero, allowing or disallowing F emulation through invisible traps to M-mode.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Vector state. It must not be read-only zero when vector registers are implemented; with S-mode but no vector registers, it may optionally be read-only zero.
VS (bits 10:9) — Vector state. It must not be read-only zero when vector registers are implemented; with S-mode but no vector registers, it may optionally be read-only zero.
The extension state is off; using the associated extension state traps or is unavailable.
The extension state is in its initial state.
The extension state matches the saved context in memory.
The extension state may have been modified and typically must be saved on context switch.
Privilege mode before entering the S-mode trap; SRET sets this bit to 0 after return.
SPP (bit 8) — Privilege mode before entering the S-mode trap; SRET sets this bit to 0 after return.
Previous privilege before the S-mode trap was User; SRET returns to U-mode.
Previous privilege before the S-mode trap was Supervisor; SRET returns to S-mode.
Controls endianness of explicit U-mode memory accesses; an implementation may make it a read-only copy of S-mode endianness.
UBE (bit 6) — Controls endianness of explicit U-mode memory accesses; an implementation may make it a read-only copy of S-mode endianness.
U-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
U-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
Saved SIE value before entering an S-mode trap.
SPIE (bit 5) — Saved SIE value before entering an S-mode trap.
SIE was 0 before the S-mode trap, or the saved post-return interrupt state is disabled.
SIE was 1 before the S-mode trap and SRET can restore it under the rules.
Global interrupt enable for S-mode; when running in U-mode, this bit is ignored and supervisor-level interrupts are globally enabled.
SIE (bit 1) — Global interrupt enable for S-mode; when running in U-mode, this bit is ignored and supervisor-level interrupts are globally enabled.
When currently running in S-mode, global supervisor interrupts are disabled.
When currently running in S-mode, global supervisor interrupts are enabled; delivery also depends on sie/sip.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bits 62:34) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bits 31:25) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bits 22:20) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bit 17) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bits 12:11) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bit 7) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bits 4:2) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Reserved bits; writes preserve their values and software ignores values read.
WPRI (bit 0) — Reserved bits; writes preserve their values and software ignores values read.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
sstatus is a RW CSR in supervisor status, trap, and interrupt csrs at 0x100. Check privilege and implemented extensions before interpreting its bit fields.
Read/write sstatus using csrr/csrw/csrs/csrc instructions. Ref: RISC-V Privileged Architecture §2.8
sstatus is the restricted view of S-mode-relevant mstatus fields. S-mode interrupt delivery depends on the current privilege mode, sstatus.SIE, and the corresponding pending/enabled bits in sip/sie; do not reduce it to mstatus.MIE control. On trap entry, hardware saves SIE to SPIE and clears SIE; sret restores SIE from SPIE.
SIE(bit1) S-mode interrupt enable | SPIE(bit5) saved SIE before trap | SPP(bit8) pre-trap privilege (0=U,1=S) | SUM(bit18) permit S-mode access to U-mode memory | MXR(bit19) make executable pages readable
During initialization or the relevant privileged flow, software reads sstatus to observe the current state.
Modify only the target fields while preserving all other bits.
Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records sstatus as Supervisor. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WPRI, or reserved fields.