Additional machine status register (RV32 only); holds extra fields of mstatus that don't fit in 32 bits.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bits 31:11) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
M-mode-disable-trap bit (Smdbltrp); in RV32 corresponds to RV64 mstatus[42].
MDT (bit 10) — M-mode-disable-trap bit (Smdbltrp); in RV32 corresponds to RV64 mstatus[42].
Machine double-trap guard is not set.
Machine double-trap guard is set; later M-mode traps follow Smdbltrp rules.
Machine Previous Expected Landing Pad state defined by Zicfilp; on RV32 this corresponds to RV64 mstatus[41].
MPELP (bit 9) — Machine Previous Expected Landing Pad state defined by Zicfilp; on RV32 this corresponds to RV64 mstatus[41].
No landing-pad instruction is expected.
A landing-pad instruction is expected.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bit 8) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Previous virtualization mode defined by the Hypervisor extension; in RV32 corresponds to RV64 mstatus[39]. This field does not exist without the Hypervisor extension.
MPV (bit 7) — Previous virtualization mode defined by the Hypervisor extension; in RV32 corresponds to RV64 mstatus[39]. This field does not exist without the Hypervisor extension.
Execution before the M-mode trap was not virtualized.
Execution before the M-mode trap was virtualized.
Defined by the Hypervisor extension; indicates whether mtval contains a guest virtual address and corresponds to RV64 mstatus[38]. This field does not exist without the Hypervisor extension.
GVA (bit 6) — Defined by the Hypervisor extension; indicates whether mtval contains a guest virtual address and corresponds to RV64 mstatus[38]. This field does not exist without the Hypervisor extension.
The address in mtval is not a guest virtual address.
The address in mtval is a guest virtual address.
Controls non-instruction-fetch M-mode memory-access endianness when MPRV=0; in RV32 corresponds to RV64 mstatus[37].
MBE (bit 5) — Controls non-instruction-fetch M-mode memory-access endianness when MPRV=0; in RV32 corresponds to RV64 mstatus[37].
M-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
M-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
S-mode explicit memory-access endianness control; read-only zero if S-mode is not implemented and may be a read-only copy of MBE; in RV32 corresponds to RV64 mstatus[36].
SBE (bit 4) — S-mode explicit memory-access endianness control; read-only zero if S-mode is not implemented and may be a read-only copy of MBE; in RV32 corresponds to RV64 mstatus[36].
S-mode explicit memory accesses are little-endian; instruction fetch is not affected by this bit.
S-mode explicit memory accesses are big-endian; instruction fetch is not affected by this bit.
Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
WPRI (bits 3:0) — Reserved WPRI bits; software should preserve their values on writes and ignore their values on reads.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
mstatush exists only for RV32 and carries high-order mstatus fields. The official specification states that SD, SXL, and UXL do not exist in mstatush.
During initialization or the relevant privileged flow, software reads mstatush to observe the current state.
Modify only the target fields while preserving all other bits.
Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.
Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records mstatush as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.
Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.