CSR Bit Fields

RISC-V vsip CSR Register

Address 0x244Privilege Hypervisor direct / VS aliasAccess HRW / VSXLEN; 64-bit state with AIA (RV32 high half through vsiph)Hypervisor and virtualization CSRs

vsip is the guest-visible VS interrupt-pending CSR; it substitutes for sip when V=1, standard bits alias or read zero according to hideleg, and AIA widens the state to 64 bits.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand vsip By Bit Fields

9 key fields
63:14

Platform/AIA interrupt pending

WARL/Alias/RO0

Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.

Platform/AIA interrupt pending (bits 63:14) — Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.

What This Field Controls

  • - Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
13

LCOFIP

Alias/RO0

With Shlcofideleg and hideleg[13]=1, this aliases sip.LCOFIP; otherwise it is read-only zero under the base H rules. Under AIA, hideleg[13]=0 and hvien[13]=1 instead make it an alias of hvip[13]; if both are zero it is read-only zero.

LCOFIP (bit 13) — With Shlcofideleg and hideleg[13]=1, this aliases sip.LCOFIP; otherwise it is read-only zero under the base H rules. Under AIA, hideleg[13]=0 and hvien[13]=1 instead make it an alias of hvip[13]; if both are zero it is read-only zero.

What This Field Controls

  • - With Shlcofideleg and hideleg[13]=1, this aliases sip.LCOFIP; otherwise it is read-only zero under the base H rules. Under AIA, hideleg[13]=0 and hvien[13]=1 instead make it an alias of hvip[13]; if both are zero it is read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
12:10

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 12:10) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
9

SEIP

Read-only alias/RO0

Read-only alias of hip.VSEIP when hideleg[10]=1; otherwise read-only zero.

SEIP (bit 9) — Read-only alias of hip.VSEIP when hideleg[10]=1; otherwise read-only zero.

What This Field Controls

  • - Read-only alias of hip.VSEIP when hideleg[10]=1; otherwise read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
8:6

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 8:6) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
5

STIP

Read-only alias/RO0

Read-only alias of hip.VSTIP when hideleg[6]=1; otherwise read-only zero. hip.VSTIP can combine hvip.VSTIP with the Sstc vstimecmp signal.

STIP (bit 5) — Read-only alias of hip.VSTIP when hideleg[6]=1; otherwise read-only zero. hip.VSTIP can combine hvip.VSTIP with the Sstc vstimecmp signal.

What This Field Controls

  • - Read-only alias of hip.VSTIP when hideleg[6]=1; otherwise read-only zero. hip.VSTIP can combine hvip.VSTIP with the Sstc vstimecmp signal.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
4:2

Reserved

RO0

Standard reserved bits that read as zero.

Reserved (bits 4:2) — Standard reserved bits that read as zero.

What This Field Controls

  • - Standard reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
1

SSIP

Read-write alias/RO0

Writable alias of hip.VSSIP when hideleg[2]=1; otherwise read-only zero. hip.VSSIP is itself an alias of hvip.VSSIP.

SSIP (bit 1) — Writable alias of hip.VSSIP when hideleg[2]=1; otherwise read-only zero. hip.VSSIP is itself an alias of hvip.VSSIP.

What This Field Controls

  • - Writable alias of hip.VSSIP when hideleg[2]=1; otherwise read-only zero. hip.VSSIP is itself an alias of hvip.VSSIP.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
0

Reserved

RO0

Standard reserved bit that reads as zero.

Reserved (bit 0) — Standard reserved bit that reads as zero.

What This Field Controls

  • - Standard reserved bit that reads as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Open Official Manual
Official Basis & Search Notes

vsip exposes VS interrupt-pending state to a guest. hideleg determines whether each standard bit aliases the corresponding hip bit or reads zero; AIA adds the hvien/hvip path for causes 13-63.

vsip is HRW at 0x244; base H makes it VSXLEN bits wide, while AIA widens the state to 64 bits and provides RV32 vsiph.
When hideleg[10/6/2]=1, SEIP/STIP/SSIP alias hip.VSEIP/VSTIP/VSSIP respectively; otherwise they are read-only zero.
For AIA causes 13-63, hideleg selects a sip alias first, otherwise hvien can select an hvip alias; if both are zero, the bit is read-only zero. hvictl.VTI can also intercept guest sip accesses and CSR writes that may clear non-SEIP pending bits.

What To Check First When Reading This CSR

  • - vsip's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - The H extension defines VSXLEN-bit vsip; AIA widens the vsip state to 64 bits and provides RV32 high-half access through vsiph.

Risk Checks Before Writing

  • - Standard SEIP and STIP are read-only aliases; SSIP is a writable alias when delegated by hideleg. For AIA causes 13-63, writability follows the selected sip or hvip source.
  • - Under AIA, hvictl.VTI=1 makes an explicit VS-mode access to sip raise a virtual-instruction exception; a write to any CSR that may clear a non-SEIP vsip bit also raises it, regardless of the written value or current pending state.

Put It Back Into A Real Flow

1

M/HS software may access the VS copy through the separate CSR address.

2

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

3

Under base H, pending state, vsie, and vsstatus.SIE/current mode govern VS interrupts; under AIA, a VS-level interrupt is pending if and only if vstopi is nonzero.

FAQ

Can VS-mode directly access vsip's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vsip mainly hold?

vsip exposes guest-visible VS interrupt-pending bits; whether each bit is an alias, writable, or read-only zero depends on hideleg, implemented extensions, and AIA hvien rules.