RISC-V vsip CSR Register

Address 0x244Privilege Hypervisor direct / VS aliasAccess HRW / 64-bit with AIA; otherwise follows VSXLEN supervisor semanticsHypervisor and virtualization CSRs

vsip holds virtual supervisor interrupt-pending bits, widened to 64 bits by AIA.

Related Search Terms

vsip CSR vsip 0x244 vsip interrupt vsip AIA VS interrupt

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

IP63:0RW

Field Map

Understand vsip By Bit Fields

1 key fields

63:0

IP

vsip virtual supervisor interrupt-pending bits. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

IP (bits 63:0) — vsip virtual supervisor interrupt-pending bits. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

What This Field Controls

- vsip virtual supervisor interrupt-pending bits. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

Common Values

0Not pending

Only for officially defined virtual supervisor interrupt bits: 0 means that bit is not pending; undefined, reserved, or read-only-zero bits follow the official rules.

1Pending

Only for officially defined virtual supervisor interrupt bits: 1 means that bit is pending; delivery also depends on vsie and vsstatus.SIE. Undefined or reserved bits have no fixed 1=pending meaning.

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Official Basis & Search Notes

vsip is a VS virtual-interrupt CSR. The separate CSR address is for M/HS-side management; when V=1, guest access to the corresponding supervisor CSR is substituted with VS state unless an extension specifies otherwise.

vsip address, access class, and width are checked against the official CSR tables: 0x244, HRW, 64-bit with AIA; otherwise follows VSXLEN supervisor semantics.

AIA widens VS interrupt-enable/pending state to 64 bits and provides RV32 high-half CSRs.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Hypervisor extension RISC-V Advanced Interrupt Architecture CSR chapter

What To Check First When Reading This CSR

- vsip's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
- Before reading it, confirm that the defining extension such as H, AIA, Sstc, Smstateen, or Smcsrind is implemented.

Risk Checks Before Writing

- When writing vsip, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

M/HS software may access the VS copy through the separate CSR address.

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

Update only official fields and do not treat VS state as ordinary HS supervisor state.

FAQ

Can VS-mode directly access vsip's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vsip mainly hold?

vsip holds virtual supervisor interrupt-pending bits, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.