Platform/AIA interrupt pending
WARL/Alias/RO0Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.
Platform/AIA interrupt pending (bits 63:14) — Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.
What This Field Controls
- - Without AIA, bits 16 and above within VSXLEN are platform-use WARL pending bits as implemented, while bits 15:14 are read-only zero. For AIA causes 14-63, hideleg[i]=1 makes vsip[i] an alias of sip[i]; otherwise hvien[i]=1 makes it an alias of hvip[i]; if both are zero it is read-only zero. RV32 accesses AIA bits 63:32 through vsiph.
Common Values
This field is better understood together with surrounding context than as a fixed memorized enumeration.
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