How is MRET different from an ordinary JALR return?
MRET takes its target from mepc and restores privilege and interrupt-enable state. It returns using trap state rather than taking its target from an integer source register.
MRET
RISC-V MRET Instruction Details
Instruction ManualI-typeMachine trap return: pc<-mepc, return mode from mstatus.MPP and (with H) MPV, MIE<-MPIE, with MPIE, MPP, MPV, and related state updated as specified by the privileged architecture.
Instruction Syntax
mret
Operand Breakdown
RV32/RV64 machine-level privileged instruction; fixed 32-bit SYSTEM encoding 0x30200073 with no explicit operands.
M-mode only: fixed rd/rs1=x0 fields are not integer operands. Execution below M-mode raises an illegal-instruction exception.
First select the return mode from MPP and, with H, MPV; MPV is ignored for MPP=M. Restore PC and MIE←MPIE, set MPIE←1 and MPP to the least-privileged supported mode; clear MPV with H and MPRV on a return below M.
mepc[0] is always zero; IALIGN=32 masks bit 1 on the implicit read. xRET may but need not clear an LR reservation. Extension-conditioned MDT, SDT and ELP state follows the relevant rules.
PrivilegedSystem & Privileged
Instruction Behavior
MRET is the privileged return instruction used by a machine-mode trap handler. It first determines the return mode from MPP and MPV in mstatus (or mstatush on RV32), then clears MPV, restores MIE from MPIE, sets MPIE to 1 and MPP to the least-privileged supported mode, and finally sets pc to mepc; a return below M also clears MPRV. MPV participates in virtualized return-mode selection only with H and is ignored when MPP=M. MRET is legal only in M-mode, and lower-privilege execution raises an illegal-instruction exception.
MRET Decode And Return Animation
Starts from the fixed SYSTEM encoding, then shows xRET permission checks, EPC-to-PC restoration, and previous interrupt-enable / previous privilege field updates.
no explicit operands
mretmret
Execution Contextmode=M
31..20
19..15
14..12
11..7
6..0
001100000010
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
instruction
0x30200073
opcode
1110011 -> SYSTEM
funct3
000 -> privileged return form
fixed
funct12=001100000010, rs1=x0, rd=x0
permission
M-mode may execute MRET
mepc
mepc=0x0000000000008040 -> pc=0x0000000000008040 (bit 1 masked)
MPP
MPP=S, MPV=0 -> privilege=S
MPV (H)
0 -> 0
MPIE
MIE=MPIE=1; MPIE=1
final
Return state not committed yet
Assumes execution in M-mode with U/S/M supported (final MPP=U). The H checkbox selects the MPV=1 virtualization branch. Input is the stored mepc value with bit 0 zero; the implicit read masks bit 1 at IALIGN=32. Executing MRET below M-mode raises an illegal-instruction exception. Steps are teaching views.
This animation shows core xRET state and MRET's MPV return branch; it does not model extension-conditioned state such as MDT or ELP, OS scheduling, handler body, pipeline behavior, latency, or platform policy.
Quick Understanding & Search Notes
MRET restores the return context saved for a machine-mode trap handler: PC comes from mepc, return mode from MPP and (with H) MPV, and interrupt enable from MPIE. It is not a function return or ordinary jump.
In the SYSTEM encoding, funct12=001100000010, rs1=x0, rd=x0, and funct3=000.
After execution, MPP and (with H) MPV first select the return mode; then MPV<-0, MIE<-MPIE, MPIE<-1, MPP<-least-privileged supported mode, and pc<-mepc.
If returning to a mode below M, MPRV is cleared; xRET may but need not clear an LR/SC reservation.
mepc[0] is always zero; with IALIGN=32, the implicit MRET read also masks mepc[1].
Common Usage Scenarios
M-mode handler return
Understand this scenario with real code like «mret # Return from M-mode trap».
Firmware/SEE return
Understand this scenario with real code like «mret # Return from M-mode trap».
Pre-Use Checklist
Syntax Check
- RV32/RV64 machine-level privileged instruction; fixed 32-bit SYSTEM encoding 0x30200073 with no explicit operands.
- M-mode only: fixed rd/rs1=x0 fields are not integer operands. Execution below M-mode raises an illegal-instruction exception.
Semantic Check
- First select the return mode from MPP and, with H, MPV; MPV is ignored for MPP=M. Restore PC and MIE←MPIE, set MPIE←1 and MPP to the least-privileged supported mode; clear MPV with H and MPRV on a return below M.
- mepc[0] is always zero; IALIGN=32 masks bit 1 on the implicit read. xRET may but need not clear an LR reservation. Extension-conditioned MDT, SDT and ELP state follows the relevant rules.
Pitfalls / Common Confusions
Legal only in M-mode; execution in S/U-mode raises an illegal-instruction exception.
MRET is not an ordinary jump: the target PC comes from mepc, and return mode plus interrupt enable come from mstatus.MPP/MPV/MPIE; MPV is ignored when MPP=M.
When returning to a mode below M, MPRV is cleared; do not assume the handler keeps its prior MPRV data-access setting.
xRET may clear an LR/SC reservation but is not required to; handlers should explicitly clear it if needed.
FAQ
Does MRET write an integer register?
No. Its encoding fixes rd to x0; its architectural effects are updates to PC, current privilege, and relevant mstatus fields.