Does MNRET change MRET or SRET?
No. MRET/SRET neither depend on nor change NMIE. MNRET performs RNMI return.
MNRET
RISC-V MNRET Instruction Details
Instruction ManualSYSTEM I-type fieldsReturn from an Smrnmi RNMI handler: restore pc from mnepc and privilege/virtualization state from mnstatus.
Instruction Syntax
mnret
Operand Breakdown
Smrnmi 1.0; M-mode only; RV32/RV64 fixed 32-bit SYSTEM encoding 0x70200073, with no explicit operands or variable immediate.
funct12=011100000010, rs1=00000, funct3=000, rd=00000, opcode=1110011.
PC comes from mnepc, privilege/virtualization mode from mnstatus.MNPP/MNPV; NMIE becomes 1 and return below M clears MPRV.
On implementations with switchable IALIGN, the implicit mnepc read masks bit 1 at IALIGN=32; bit 0 is always zero. See specification focus for conditional ELP/double-trap state.
PrivilegedSmrnmiSystem & Privilege
Related Search Terms
Instruction Behavior
MNRET is the M-mode-only return instruction added by Smrnmi. It uses mnepc and mnstatus to return to the interrupted program counter, privilege mode, and virtualization mode, sets mnstatus.NMIE, and clears mstatus.MPRV if returning below M-mode.
MNRET Decode And Return Animation
Shows only Smrnmi-defined mnepc, MNPP/MNPV, NMIE, and conditional MPRV state.
mnretAssumes Smrnmi, U/S/M and H, with switchable IALIGN. Input is the stored MXLEN-bit mnepc; bit 0 must be zero. MNPV is ignored for MNPP=M. Models the core return; conditional Zicfilp ELP and Smdbltrp/Ssdbltrp MDT/SDT updates are not modeled. Steps are teaching views.
31..20
19..15
14..12
11..7
6..0
011100000010
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
instruction
0x70200073
permission
M-mode -> execute
mnepc
0x0000000000008042 -> 0x0000000000008040 (bit 1 masked)
mnstatus
MNPP=S, MNPV=0 -> S
architectural state
MNRET state not committed
Quick Understanding & Search Notes
MNRET executes only in M-mode, restores the RNMI-interrupted context using mnepc and mnstatus, and sets NMIE=1.
Smrnmi 1.0; M-mode only.
PC comes from mnepc; MNPP/MNPV select privilege/virtualization mode; NMIE becomes 1.
Return below M clears MPRV.
Stored mnepc is MXLEN-wide with bit 0 zero; switchable IALIGN=32 masks bit 1 on implicit reads.
With Zicfilp: ELP becomes yLPE AND MNPELP. With double-trap state: return below M clears MDT; U/VS/VU clears sstatus.SDT; VU also clears vsstatus.SDT.
Common Usage Scenarios
RNMI handler return
Assume Smrnmi, execution in M-mode, switchable IALIGN, stored mnepc=0x8042, current IALIGN=32, MNPP=S and MNPV=0. MNRET returns to PC=0x8040 in S-mode, sets NMIE=1 and clears MPRV. With IALIGN=16, PC=0x8042. Conditional ELP/double-trap state is not modeled here.
Pre-Use Checklist
Syntax Check
- Smrnmi 1.0; M-mode only; RV32/RV64 fixed 32-bit SYSTEM encoding 0x70200073, with no explicit operands or variable immediate.
- funct12=011100000010, rs1=00000, funct3=000, rd=00000, opcode=1110011.
Semantic Check
- PC comes from mnepc, privilege/virtualization mode from mnstatus.MNPP/MNPV; NMIE becomes 1 and return below M clears MPRV.
- On implementations with switchable IALIGN, the implicit mnepc read masks bit 1 at IALIGN=32; bit 0 is always zero. See specification focus for conditional ELP/double-trap state.
Pitfalls / Common Confusions
Requires Smrnmi and is M-mode only.
It is for resumable non-maskable interrupt handlers, not a general trap return.
MRET and SRET are unaffected by mnstatus.NMIE; use MNRET to resume from RNMI.