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SRET

RISC-V SRET Instruction Details

Instruction ManualI-type

Supervisor trap return: pc<-sepc, privilege<-sstatus.SPP, SIE<-SPIE; in S-mode, TSR=1 makes SRET raise an illegal-instruction exception.

Instruction Syntax

sret
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
PrivilegedSystem & Privileged
Related Search Terms
SRET instructionRISC-V SRETsret encodingsret trap returnsepc restoresstatus SPPTSR SRET

Instruction Behavior

SRET is the privileged return instruction used by a supervisor trap handler. It sets pc to sepc, restores the current privilege mode from sstatus.SPP, restores SIE from SPIE, sets SPIE to 1, and clears SPP. SRET may execute in S-mode or a higher privilege mode; if mstatus.TSR=1, S-mode execution raises an illegal-instruction exception, and U-mode execution also raises an illegal-instruction exception.

SRET Decode And Return Animation

Starts from the fixed SYSTEM encoding, then shows xRET permission checks, EPC-to-PC restoration, and previous interrupt-enable / previous privilege field updates.

no explicit operands
sretsret
Execution Contextmode=S
31..20
19..15
14..12
11..7
6..0
000100000010
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
instruction
0x10200073
opcode
1110011 -> SYSTEM
funct3
000 -> privileged return form
fixed
funct12=000100000010, rs1=x0, rd=x0
permission
S-mode may execute SRET
sepc
sepc=0x0000000000004040 -> pc
SPP
SPP=U -> privilege=U
SPIE
SIE=SPIE=1; SPIE=1
final
0x0000000000004040; mode=U

This animation shows only privileged-architecture ISA-visible return state; it does not simulate OS scheduling, handler body, pipeline behavior, latency, or platform policy.

Quick Understanding & Search Notes

SRET restores the return context saved for a supervisor trap handler: PC comes from sepc, return privilege from SPP, and interrupt enable from SPIE. TSR can make SRET in S-mode trap as an illegal instruction.

In the SYSTEM encoding, funct12=000100000010, rs1=x0, rd=x0, and funct3=000.
After execution, pc<-sepc, privilege<-SPP, SIE<-SPIE, SPIE<-1, and SPP<-0.
In S-mode, mstatus.TSR=1 makes SRET raise an illegal-instruction exception; M-mode execution is not constrained by that TSR check.
RISC-V Privileged Architecture Manual: Supervisor-Level ISA / SRETRISC-V Privileged Architecture Manual: mstatus TSR

Common Usage Scenarios

OS kernel exception/interrupt return

Understand this scenario with real code like «sret # Return from S-mode trap».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Execution in U-mode raises an illegal-instruction exception.
When mstatus.TSR=1, S-mode execution of SRET raises an illegal-instruction exception.
SRET is not an ordinary jump: the target PC comes from sepc, and return privilege plus interrupt enable come from SPP/SPIE.
xRET may clear an LR/SC reservation but is not required to; handlers should explicitly clear it if needed.

FAQ

What is the main difference between SRET and MRET?

SRET restores supervisor trap-return state using sepc and SPP/SPIE; MRET restores machine trap-return state using mepc and MPP/MPIE.

How does TSR affect SRET?

When mstatus.TSR=1 and SRET is executed in S-mode, the specification requires an illegal-instruction exception instead of completing the return.