What is the main difference between SRET and MRET?
On the V=0 base path, SRET uses sepc and SPP/SPIE while MRET uses mepc and MPP/MPIE. Virtualized SRET additionally follows the dedicated hstatus/vsstatus/vsepc rules.
SRET
RISC-V SRET Instruction Details
Instruction ManualI-typeSupervisor trap return: on the V=0 base path pc<-sepc, privilege is restored from sstatus.SPP, and SIE<-SPIE; in S-mode, TSR=1 raises an illegal-instruction exception. Virtualized paths instead follow the hstatus/vsstatus/vsepc rules.
Instruction Syntax
sret
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
PrivilegedSystem & Privileged
Instruction Behavior
SRET is the supervisor trap-return instruction. On the non-virtualized V=0 path it first determines the return mode from hstatus.SPV and sstatus.SPP, then clears hstatus.SPV and SPP, sets SIE<-SPIE and SPIE<-1, and finally sets pc<-sepc; without H this reduces to the usual SPP/SPIE/sepc restore. The V=1 VS-mode path instead uses vsstatus.SPP/SPIE and vsepc. With mstatus.TSR=1, execution in S-mode raises an illegal-instruction exception; executing an xRET below its privilege mode also raises an illegal-instruction exception.
SRET Decode And Return Animation
Starts from the fixed SYSTEM encoding and shows the V=0 base SRET permission check, sepc-to-PC restoration, and SPP/SPIE state updates.
no explicit operands
sretsret
Execution Contextmode=S
31..20
19..15
14..12
11..7
6..0
000100000010
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
instruction
0x10200073
opcode
1110011 -> SYSTEM
funct3
000 -> privileged return form
fixed
funct12=000100000010, rs1=x0, rd=x0
permission
S-mode may execute SRET
sepc
sepc=0x0000000000004040 -> pc
SPP
SPP=U -> privilege=U
SPIE
SIE=SPIE=1; SPIE=1
final
0x0000000000004040; mode=U
This SRET animation models only the V=0 base path without H virtualization. It does not model hstatus.SPV, VS-mode vsstatus/vsepc, VTSR, or Ssdbltrp state, and must not be used as a virtualized-return model.
Quick Understanding & Search Notes
On the V=0 path, SRET restores a trap handler's saved return context: PC comes from sepc, return privilege from SPP, and interrupt enable from SPIE. TSR can make SRET in S-mode trap as an illegal instruction; VS-mode uses its dedicated vsepc/vsstatus rules.
In the SYSTEM encoding, funct12=000100000010, rs1=x0, rd=x0, and funct3=000.
On the V=0 path, pc<-sepc, privilege is selected from hstatus.SPV/SPP, SIE<-SPIE, SPIE<-1, and SPP<-0; the VS-mode path uses vsepc/vsstatus.
In S-mode, mstatus.TSR=1 makes SRET raise an illegal-instruction exception; M-mode execution is not constrained by that TSR check.
Common Usage Scenarios
OS kernel exception/interrupt return
Understand this scenario with real code like «sret # Return from S-mode trap».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
Execution in U-mode raises an illegal-instruction exception.
When mstatus.TSR=1, S-mode execution of SRET raises an illegal-instruction exception.
The V=0 base path is not an ordinary jump: its target PC comes from sepc, and return privilege plus interrupt enable come from SPP/SPIE; the VS-mode path uses vsepc/vsstatus.
xRET may clear an LR/SC reservation but is not required to; handlers should explicitly clear it if needed.
FAQ
How does TSR affect SRET?
When mstatus.TSR=1 and SRET is executed in S-mode, the specification requires an illegal-instruction exception instead of completing the return.