RVOPcode
Home/Instructions/Supervisor-mode Return
SRET

RISC-V SRET Instruction Details

Instruction ManualI-type

Supervisor trap return: pc<-sepc, privilege<-sstatus.SPP, SIE<-SPIE; with TSR=1, S-mode execution raises an illegal-instruction exception.

Instruction Syntax

sret
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
PrivilegedSystem & Privileged
Related Search Terms
SRET instructionRISC-V SRETsret syntaxsret encodingsret privilegedsupervisor trap return

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

SRET uses opcode 1110011 (0x73), funct3 000, funct12 000100000010. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 1110011 (0x73)
funct3: 000 (0x0)
funct12: 000100000010 (0x102)

Instruction Behavior

SRET returns from a supervisor trap handler: pc is set to sepc, the current privilege mode is restored from sstatus.SPP, SIE is restored from SPIE, SPIE is set to 1, and SPP is cleared to 0. SRET can execute in S-mode or a higher privilege mode; if mstatus.TSR=1, S-mode execution raises an illegal-instruction exception. U-mode execution also raises an illegal-instruction exception.

Quick Understanding & Search Notes

SRET is a system-level instruction defined by the privileged architecture. This page covers architectural semantics only, not platform firmware policy.

Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
Executing at an unsupported privilege level or without the required extension raises the specified exception.
RISC-V Privileged Architecture Manual, Supervisor-Level ISA

Common Usage Scenarios

OS kernel exception/interrupt return

Understand this scenario with real code like «sret # Return from S-mode trap».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Execution in U-mode raises an illegal-instruction exception.
When mstatus.TSR=1, S-mode execution of SRET raises an illegal-instruction exception.
xRET may clear an LR/SC reservation but is not required to; handlers should explicitly clear it if needed.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.