What is the main difference between SRET and MRET?
On the V=0 base path, SRET uses sepc and SPP/SPIE while MRET uses mepc and MPP/MPIE. Virtualized SRET additionally follows the dedicated hstatus/vsstatus/vsepc rules.
SRET
RISC-V SRET Instruction Details
Instruction ManualI-typeSupervisor trap return: without H, restore PC, mode and SIE from sepc and SPP/SPIE, clear SPP and set SPIE; TSR restricts S-mode execution.
Instruction Syntax
sret
Operand Breakdown
No explicit assembly operands; fixed 32-bit SYSTEM encoding 0x10200073, rs1/rd=00000 and funct3=000.
Requires S-mode. The base path executes in S/M-mode; TSR=1 in S-mode raises illegal-instruction.
Without H, SPP selects U/S; SIE←SPIE, SPIE←1, SPP←0, PC←sepc, and MPRV is cleared.
sepc[0]=0. With switchable IALIGN, an IALIGN=32 implicit read masks bit 1. H and conditioned SDT/ELP state follow separate rules.
PrivilegedSystem & Privileged
Extension condition: Requires S-mode; executable in S-mode or M-mode. H adds separate VS/VU return and VTSR rules.
Instruction Behavior
SRET has no explicit operands and is encoded as 0x10200073. Without H, sstatus.SPP selects U (0) or S (1); SIE←SPIE, SPIE←1, SPP←0, PC←sepc, and mstatus.MPRV is cleared. sepc[0] is always zero; on implementations with switchable IALIGN, the implicit read masks bit 1 at IALIGN=32. S-mode execution with TSR=1 raises an illegal-instruction exception. M-mode is not constrained by that TSR check; execution below S is illegal. With H, V=0 selects the return mode from hstatus.SPV/SPP and clears SPV; V=1 uses vsstatus/vsepc. VTSR and extension-conditioned state rules still apply.
SRET Decode And Return Animation
Starts from the fixed SYSTEM encoding and shows the V=0 base SRET permission check, sepc-to-PC restoration, and SPP/SPIE state updates.
no explicit operands
sretsret
Execution Contextmode=S
31..20
19..15
14..12
11..7
6..0
000100000010
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
instruction
0x10200073
opcode
1110011 -> SYSTEM
funct3
000 -> privileged return form
fixed
funct12=000100000010, rs1=x0, rd=x0
permission
S-mode may execute SRET
sepc
sepc=0x0000000000004040 -> pc=0x0000000000004040 (bit 1 masked)
SPP
SPP=U -> privilege=U
SPIE
SIE=SPIE=1; SPIE=1
final
Return state not committed yet
This SRET animation assumes U/S/M and models only V=0 without H. Input is the stored XLEN-bit sepc with bit 0 zero; the implicit read masks bit 1 at IALIGN=32. A successful return clears MPRV. It does not model hstatus.SPV, VS-mode vsstatus/vsepc, VTSR, or extension-conditioned SDT/ELP state, and must not be used as a virtualized-return model.
Quick Understanding & Search Notes
Supervisor trap return: without H, restore PC, mode and SIE from sepc and SPP/SPIE, clear SPP and set SPIE; TSR restricts S-mode execution.
In the SYSTEM encoding, funct12=000100000010, rs1=x0, rd=x0, and funct3=000.
On the H-enabled V=0 path, pc<-sepc, privilege is selected from hstatus.SPV/SPP, SIE<-SPIE, SPIE<-1, and SPP<-0; the VS-mode path uses vsepc/vsstatus.
In S-mode, mstatus.TSR=1 makes SRET raise an illegal-instruction exception; M-mode execution is not constrained by that TSR check.
A successful return below M clears mstatus.MPRV; the implicit sepc read follows the IALIGN bit-1 masking rule.
Common Usage Scenarios
OS kernel exception/interrupt return
Assume no H, U/S/M implemented, switchable IALIGN, execution in S with TSR=0, sepc=0x4042, IALIGN=32, SPP=U and SPIE=1: sret sets PC=0x4040, mode U, SIE=1, SPIE=1, SPP=0 and MPRV=0. Extension state such as SDT/ELP is omitted.
Pre-Use Checklist
Syntax Check
- No explicit assembly operands; fixed 32-bit SYSTEM encoding 0x10200073, rs1/rd=00000 and funct3=000.
- Requires S-mode. The base path executes in S/M-mode; TSR=1 in S-mode raises illegal-instruction.
Semantic Check
- Without H, SPP selects U/S; SIE←SPIE, SPIE←1, SPP←0, PC←sepc, and MPRV is cleared.
- sepc[0]=0. With switchable IALIGN, an IALIGN=32 implicit read masks bit 1. H and conditioned SDT/ELP state follow separate rules.
Pitfalls / Common Confusions
Execution in U-mode raises an illegal-instruction exception.
When mstatus.TSR=1, S-mode execution of SRET raises an illegal-instruction exception.
The V=0 base path is not an ordinary jump: its target PC comes from sepc, and return privilege plus interrupt enable come from SPP/SPIE; the VS-mode path uses vsepc/vsstatus.
xRET may clear an LR/SC reservation but is not required to; handlers should explicitly clear it if needed.
FAQ
How does TSR affect SRET?
When mstatus.TSR=1 and SRET is executed in S-mode, the specification requires an illegal-instruction exception instead of completing the return.