Are CSR instructions memory atomics?
No. Atomic here means the CSR read-modify-write is one instruction, not an AMO to memory.
CSRRWI
RISC-V CSRRWI Instruction Details
Instruction ManualI-typeAtomically swap CSR and zero-extended 5-bit immediate: read old CSR value into rd, write uimm to the CSR
Instruction Syntax
csrrwi rd, csr, uimm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicsrCSR OperationSystem
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
CSRRWI uses opcode 1110011 (0x73), funct3 101. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 1110011 (0x73)
funct3: 101 (0x5)
Instruction Behavior
CSRRWI is the immediate variant of CSRRW: it reads the old CSR value, zero-extends it to XLEN, writes it to rd, then writes the 5-bit unsigned immediate uimm[4:0], zero-extended to XLEN, into the CSR. If rd=x0, the instruction does not read the CSR and does not trigger CSR read side effects. The immediate can encode only 0..31; larger values require CSRRW with an integer register. The assembler pseudo-instruction CSRWI(csr, uimm) is encoded as CSRRWI x0, csr, uimm.
Quick Understanding & Search Notes
CSRRWI is a Zicsr atomic CSR read-modify-write instruction. CSR addresses are 12 bits, and whether read/write side effects occur depends on rd and on rs1 or uimm being x0/0.
CSRRWI does not read the CSR when rd=x0; but regardless of whether uimm is 0, write semantics follow the CSRRW immediate form.
uimm is a 5-bit unsigned immediate, zero-extended to XLEN before being written to the CSR.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «csrrwi x5, fflags, 3 # x5 = old fflags; fflags = 3».
System & Privilege
Understand this scenario with real code like «csrrwi x5, fflags, 3 # x5 = old fflags; fflags = 3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Immediate is only 5 bits (0–31); values >31 require CSRRW with a register
When rd=x0, CSR read is suppressed but write still executes
uimm=0 writes all zeros to the CSR, unlike CSRRSI/CSRRCI where uimm=0 means 'no write'
FAQ
What does rd=x0 change?
For CSRRW it suppresses the CSR read and read side effects; CSRRS/CSRRC still read the CSR.