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CSRRWI

RISC-V CSRRWI Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and write the zero-extended 5-bit uimm to the CSR; rd=x0 suppresses the CSR read

Instruction Syntax

csrrwi rd, csr, uimm

Operand Breakdown

Destination rd: general-purpose register receiving the result.

Source rs1: register holding the first operand.

Immediate imm: 12-bit signed value, sign-extended before operation with rs1.

ZicsrCSR OperationSystem

Related Search Terms

CSRRWI instruction RISC-V CSRRWI csrrwi syntax csrrwi encoding Zicsr CSRRWI CSR uimm write CSRRWI uimm

Instruction Behavior

CSRRWI is the immediate form of CSRRW: it reads the old CSR value, zero-extends it to XLEN for rd, then writes the zero-extended 5-bit unsigned uimm to the target CSR. If rd=x0, the instruction does not read the CSR and causes no CSR read side effects; regardless of whether uimm is 0, the write still follows CSRRWI semantics.

CSRRWI Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

uimm

csrrwi

Execution ContextXLEN

Execution Contextold CSR value

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The animation gives the example CSR no platform-specific field meaning.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00011

uimm[4:0]

101

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C01D2F3

opcode

1110011 -> SYSTEM

funct3

101 -> CSRRWI

operands

rd=t0(x5), csr=0x7C0, uimm=3

CSR read

0x7C0 -> 0x0000000A

uimm source

3 -> 0x00000003

CSR update

CSR = 0x00000003

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRWI SYSTEM encoding

CSRRWI is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C01D2F3

syntax : csrrwi t0(x5), 0x7C0, 3

result : t0(x5) = 0x0000000A; CSR = 0x00000003

CSR Bit Result

write

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRWI uses a 5-bit uimm as the source value written to the CSR. rd=x0 means no CSR read; uimm=0 still means write zero.

uimm[4:0] is zero-extended to XLEN as the write value.

When rd=x0, the CSR is not read and read side effects do not occur.

uimm=0 in CSRRWI differs from uimm=0 in CSRRSI/CSRRCI.

Read-only CSRs with CSR address bits 11 in the top two bits cannot be written by forms that perform a CSR write; such writes raise illegal-instruction, except for the zero-source read-only special case of CSRRS/CSRRC forms.

RISC-V Unprivileged ISA Manual, Zicsr

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «csrrwi x5, fflags, 3 # x5 = old fflags; fflags = 3».

System & Privilege

Understand this scenario with real code like «csrrwi x5, fflags, 3 # x5 = old fflags; fflags = 3».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is I-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

uimm is only 5 bits, with legal range 0..31.

uimm=0 writes zero; do not confuse it with the no-write special case of CSRRSI/CSRRCI.

rd=x0 suppresses the read, but not the write.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.