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CSRRWI

RISC-V CSRRWI Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and write the zero-extended 5-bit uimm to the CSR; rd=x0 suppresses the CSR read

Instruction Syntax

csrrwi rd, csr, uimm

Operand Breakdown

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=101.

rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; uimm=[19:15] is 0..31, zero-extended to XLEN.

Write the initial source value to the CSR; when rd is not x0, zero-extend the old CSR value to XLEN for rd. rd=x0 suppresses the CSR read and read side effects but still attempts a write.

uimm=0 still attempts to write zero; it is not the CSRRSI/CSRRCI no-write case.

The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

ZicsrCSR OperationSystem

Related Search Terms

CSRRWI instruction RISC-V CSRRWI csrrwi syntax csrrwi encoding Zicsr CSRRWI CSR uimm write CSRRWI uimm

Instruction Behavior

CSRRWI is the immediate form of CSRRW: it reads the old CSR value, zero-extends it to XLEN for rd, then writes the zero-extended 5-bit unsigned uimm to the target CSR. If rd=x0, the instruction does not read the CSR and causes no CSR read side effects; regardless of whether uimm is 0, the write still follows CSRRWI semantics.

CSRRWI Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

uimm

csrrwi

Execution ContextXLENold CSR value

Assume an implemented, accessible CSR with ordinary writable example bits. A read-only CSR write attempt shows an exception without committing results.

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00011

uimm[4:0]

101

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C01D2F3

opcode

1110011 -> SYSTEM

funct3

101 -> CSRRWI

operands

rd=t0(x5), csr=0x7C0, uimm=3

CSR read

0x7C0 -> 0x0000000A

uimm source

3 -> 0x00000003

CSR update

CSR = 0x00000003

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRWI SYSTEM encoding

CSRRWI is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C01D2F3

syntax : csrrwi t0(x5), 0x7C0, 3

result : t0(x5) = 0x0000000A; CSR = 0x00000003

CSR Bit Result

write

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRWI uses a 5-bit uimm as the source value written to the CSR. rd=x0 means no CSR read; uimm=0 still means write zero.

uimm[4:0] is zero-extended to XLEN as the write value.

When rd=x0, the CSR is not read and read side effects do not occur.

uimm=0 in CSRRWI differs from uimm=0 in CSRRSI/CSRRCI.

CSRRWI with uimm=0 still attempts to write zero; a concrete CSR's writable bits, readback value, and field side effects are defined by that CSR's specification.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Zicsr 2.0 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Version 20260120, CSR Address Mapping Conventions

Common Usage Scenarios

CSR Access

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrwi x5,0x7c0,3 → x5=0xa, CSR=3

System & Privilege

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits and old CSR=0xa: csrrwi x5,0x7c0,3 → x5=0xa, CSR=3

Pre-Use Checklist

Syntax Check

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=101.
rd=[11:7] selects an integer register; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate; uimm=[19:15] is 0..31, zero-extended to XLEN.

Semantic Check

Write the initial source value to the CSR; when rd is not x0, zero-extend the old CSR value to XLEN for rd. rd=x0 suppresses the CSR read and read side effects but still attempts a write.
uimm=0 still attempts to write zero; it is not the CSRRSI/CSRRCI no-write case.
The CSR must be implemented and access permitted. A read-only CSR write attempt raises illegal-instruction. Concrete field writability, readback and side-effect rules still apply.

Pitfalls / Common Confusions

uimm is only 5 bits, with legal range 0..31.

uimm=0 writes zero; do not confuse it with the no-write special case of CSRRSI/CSRRCI.

rd=x0 suppresses the read, but not the write.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.