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CSRRCI

RISC-V CSRRCI Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and clear CSR bits selected by 5-bit uimm; uimm=0 suppresses the CSR write

Instruction Syntax

csrrci rd, csr, uimm

Operand Breakdown

Destination rd: general-purpose register receiving the result.

Source rs1: register holding the first operand.

Immediate imm: 12-bit signed value, sign-extended before operation with rs1.

ZicsrCSR OperationSystem

Related Search Terms

CSRRCI instruction RISC-V CSRRCI csrrci syntax csrrci encoding Zicsr CSRRCI CSR uimm clear CSRRCI uimm

Instruction Behavior

CSRRCI is the immediate form of CSRRC: it reads the old CSR value, zero-extends it to XLEN for rd, then uses the 5-bit unsigned uimm as a low-bit mask to clear corresponding CSR bits. If uimm=0, it does not write the CSR and causes no CSR write side effects; it still reads the CSR.

CSRRCI Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

uimm

csrrci

Execution ContextXLEN

Execution Contextold CSR value

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The animation gives the example CSR no platform-specific field meaning.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00101

uimm[4:0]

111

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C02F2F3

opcode

1110011 -> SYSTEM

funct3

111 -> CSRRCI

operands

rd=t0(x5), csr=0x7C0, uimm=5

CSR read

0x7C0 -> 0x0000000A

uimm source

5 -> 0x00000005

CSR update

CSR = 0x0000000A

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRCI SYSTEM encoding

CSRRCI is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C02F2F3

syntax : csrrci t0(x5), 0x7C0, 5

result : t0(x5) = 0x0000000A; CSR = 0x0000000A

CSR Bit Result

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRCI uses 1 bits in the 5-bit uimm as a clear mask. With uimm=0 it reads the CSR but does not write it.

uimm[4:0] is a zero-extended 5-bit mask.

uimm=0 suppresses the CSR write and write side effects.

For ordinary read/write bits, CSRRCI bit operation is old_csr AND NOT uimm_mask; special CSR fields remain subject to official read-back and side-effect rules.

Read-only CSRs with CSR address bits 11 in the top two bits cannot be written by forms that perform a CSR write; such writes raise illegal-instruction, except for the zero-source read-only special case of CSRRS/CSRRC forms.

RISC-V Unprivileged ISA Manual, Zicsr

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «csrrci x5, mip, 4 # x5 = old mip; clear bit 2 in mip».

System & Privilege

Understand this scenario with real code like «csrrci x5, mip, 4 # x5 = old mip; clear bit 2 in mip».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is I-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

uimm is only a low-5-bit mask and cannot directly clear higher CSR bits.

uimm=0 is the read-only special case and performs no CSR write; a nonzero uimm directly selects only a low-5-bit clear mask, while special CSR fields remain governed by official read-back and field-side-effect rules.

CSRRCI clears by old_csr AND NOT uimm_mask; it does not write uimm itself.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.