Are CSR instructions memory atomics?
No. Atomic here means the CSR read-modify-write is one instruction, not an AMO to memory.
CSRRC
RISC-V CSRRC Instruction Details
Instruction ManualI-typeRead CSR into rd, then atomically clear bits in the CSR where rs1 has 1s; supports read-only mode
Instruction Syntax
csrrc rd, csr, rs1
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicsrCSR OperationSystem
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
CSRRC uses opcode 1110011 (0x73), funct3 011. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 1110011 (0x73)
funct3: 011 (0x3)
Instruction Behavior
CSRRC performs an atomic read-modify-write on a CSR: reads the current CSR value (zero-extended to XLEN bits) into rd, then uses rs1 as a bit mask to clear (deassert to 0) the corresponding bits in the CSR where rs1 holds 1s (provided those bits are writable). If rs1=x0, the instruction writes nothing to the CSR, causing no write side effects and no illegal-instruction exceptions on read-only CSRs. Symmetric to CSRRS, the pseudo-instruction CSRC(csr, rs1) is encoded as CSRRC x0, csr, rs1 (clear only, discard old value). Typical use: atomically clearing pending interrupt bits in mip to avoid read-modify-write races.
Quick Understanding & Search Notes
CSRRC is a Zicsr atomic CSR read-modify-write instruction. CSR addresses are 12 bits, and whether read/write side effects occur depends on rd and on rs1 or uimm being x0/0.
CSRRW does not read the CSR when rd=x0; CSRRS/CSRRC do not write the CSR when rs1=x0.
Immediate forms use a zero-extended 5-bit uimm; uimm=0 suppresses writes for CSRRSI/CSRRCI.
Accessing absent CSRs, insufficient privilege, or illegally writing read-only CSRs raises illegal-instruction.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «csrrc x5, mip, x6 # x5 = old mip; clear bits in mip per x6».
System & Privilege
Understand this scenario with real code like «csrrc x5, mip, x6 # x5 = old mip; clear bits in mip per x6».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Some CSR bits read back differently from their underlying value (e.g., pmpaddr G-bit); these may be implicitly overwritten during RMW even if corresponding rs1 bit is 0
rs1=x0 writes nothing to CSR but still triggers read side effects — this reliably implements read-only CSR access
CSRCI csr, uimm → CSRRCI x0, csr, uimm (immediate clear bits, discard old value)
FAQ
What does rd=x0 change?
For CSRRW it suppresses the CSR read and read side effects; CSRRS/CSRRC still read the CSR.