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CSRRC

RISC-V CSRRC Instruction Details

Instruction ManualI-type

Read the old CSR value into rd and atomically clear CSR bits selected by rs1; rs1=x0 suppresses the CSR write

Instruction Syntax

csrrc rd, csr, rs1

Operand Breakdown

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=011.

rd=[11:7] and rs1=[19:15] select integer registers; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate.

Zero-extend old CSR to XLEN for rd; initial rs1 selects writable bits to clear. Overlapping rd/rs1 still uses the old source value.

rs1=x0 suppresses the CSR write; zero in a non-x0 register still writes. rd=x0 discards the old-value result but never suppresses the CSR read.

CSR access permissions and field rules still apply. A read-only CSR write attempt raises illegal-instruction; rs1=x0 makes no write attempt.

ZicsrCSR OperationSystem

Related Search Terms

CSRRC instruction RISC-V CSRRC csrrc syntax csrrc encoding Zicsr CSRRC CSR clear bits CSRRC rs1 x0

Instruction Behavior

CSRRC is the Zicsr atomic CSR read-and-clear instruction: it reads the old CSR value, zero-extends it to XLEN for rd, then uses 1 bits in rs1 as a mask to clear corresponding writable CSR bits. If rs1=x0, it does not write the CSR and causes no CSR write side effects; it still reads the CSR.

CSRRC Decode And Execute Animation

Shows the Zicsr CSR read-modify-write flow: decode the SYSTEM encoding, read the CSR, compute write/set/clear semantics, then update rd and the CSR.

csr

rs1

csrrc

Execution ContextXLENold CSR valuers1 value

Assume the CSR is implemented and access is permitted; ordinary writable bits follow the mask. rs1=x0 is always zero; zero in non-x0 still attempts a write. Read-only CSR write attempts show an exception.

The CSR name/address is part of the instruction syntax; the old CSR value and rs1 example value are execution context. The example calculation treats displayed bits as writable; a concrete CSR's writable bits, readback value, and field side effects follow that CSR's specification.

31..20

19..15

14..12

11..7

6..0

011111000000

csr[11:0]

00110

rs1

011

funct3

00101

1110011

opcode

Execution Data Path

instruction

0x7C0332F3

opcode

1110011 -> SYSTEM

funct3

011 -> CSRRC

operands

rd=t0(x5), csr=0x7C0, rs1=t1(x6)

CSR read

0x7C0 -> 0x0000000A

rs1 source

t1(x6) -> 0x00000005

CSR update

CSR = 0x0000000A

rd update

t0(x5) = 0x0000000A

Current Step

Receive the 32-bit CSRRC SYSTEM encoding

CSRRC is a Zicsr I-type SYSTEM instruction; the CSR address occupies bits 31..20.

encoding: 0x7C0332F3

syntax : csrrc t0(x5), 0x7C0, t1(x6)

result : t0(x5) = 0x0000000A; CSR = 0x0000000A

CSR Bit Result

The bit view shows the CSR value computation at the selected XLEN.

This animation shows only Zicsr ISA-visible CSR reads/writes, side-effect suppression, and bit-mask semantics; it does not model concrete CSR field meanings, trap handlers, pipelines, or timing.

Quick Understanding & Search Notes

CSRRC reads the old CSR value and uses 1 bits in rs1 as a clear mask. With rs1=x0 it still reads the CSR, but does not write it.

For ordinary read/write bits, the new CSR value for CSRRC can be understood as old_csr AND NOT rs1_mask; special CSR fields are still governed by the official read-back and field-side-effect rules.

rs1=x0 suppresses the CSR write and write side effects.

CSRRC differs from CSRRS by clearing bits rather than setting them.

Read-only CSRs with CSR address bits 11 in the top two bits cannot be written by forms that perform a CSR write; such writes raise illegal-instruction, except for the zero-source read-only special case of CSRRS/CSRRC forms.

A zero value in non-x0 rs1 still writes the CSR: no per-field write side effects, but whole-CSR write side effects remain possible.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20260120

Common Usage Scenarios

Atomic & Sync

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits, old value=0xf and x6=5: csrrc x5,0x7c0,x6 gives x5=0xf and CSR=0xa.

System & Privilege

Assume implemented, accessible custom CSR 0x7c0 with ordinary writable example bits, old value=0xf and x6=5: csrrc x5,0x7c0,x6 gives x5=0xf and CSR=0xa.

Pre-Use Checklist

Syntax Check

RV32/RV64 Zicsr 2.0; 32-bit SYSTEM encoding, opcode=1110011 and funct3=011.
rd=[11:7] and rs1=[19:15] select integer registers; csr=[31:20] is a 12-bit address, not a signed arithmetic immediate.

Semantic Check

Zero-extend old CSR to XLEN for rd; initial rs1 selects writable bits to clear. Overlapping rd/rs1 still uses the old source value.
rs1=x0 suppresses the CSR write; zero in a non-x0 register still writes. rd=x0 discards the old-value result but never suppresses the CSR read.
CSR access permissions and field rules still apply. A read-only CSR write attempt raises illegal-instruction; rs1=x0 makes no write attempt.

Pitfalls / Common Confusions

rs1=x0 is the read-only special case; it clears no CSR bits.

For ordinary read/write bits, CSRRC clears only bits where rs1 has 1; however, if some CSR bits read back differently from their underlying value, the RMW writeback can affect bits where the mask is 0.

rd=x0 discards the old value, but for CSRRC it does not suppress the CSR read.

FAQ

Does atomic here mean a memory atomic?

No. In Zicsr, atomic means the CSR read and write are performed by one CSR instruction, not an AMO to a memory address.

Are rd=x0 and rs1/uimm=0 the same?

No. rd=x0 suppresses the CSR read only for CSRRW/CSRRWI; rs1=x0 or uimm=0 suppresses the CSR write only for CSRRS/CSRRC and their immediate forms.