PC-relative Branch Range
Conditional branches use the B-type immediate, a signed PC-relative offset in 2-byte units, giving an approximate reach of +/-4 KiB from the current PC.
RISC-V Unprivileged ISA, RV32I control transfer instructionsBLT
RISC-V BLT Instruction Details
Instruction ManualB-typeBranch if rs1 is less than rs2 (signed comparison)
Instruction Syntax
blt rs1, rs2, offset
Operand Breakdown
Source rs1: first comparison operand.
Source rs2: second comparison operand.
Immediate offset: 13-bit signed branch offset (bit 0 is implicitly 0, ±4 KiB range).
RV32IControl TransferBranch
Related Search Terms
Instruction Behavior
BLT compares rs1 and rs2 as signed integers and branches if rs1 < rs2 (range ±4 KiB). BGT can be synthesized by swapping BLT operands. BGE is the inverse of BLT.
BLT Decode And Execute Animation
Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.
rs1
rs2
offset
blt
,
,
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0 000000
imm[12|10:5]
00010
rs2
10000
rs1
100
funct3
0101 0
imm[4:1|11]
1100011
opcode
Execution Data Path
instruction
0x00284563
opcode
1100011 -> BRANCH
funct3
100 -> BLT
rs1 / rs2 / pc
a6(x16)=0xFFFFFFF0 / sp(x2)=0x00000002 / 0x00002000
B-imm
reassembled offset 10; bit 0 is implicit 0
condition
< -> taken
PC
pc = 0x0000200A (target)
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x00284563
syntax : blt a6(x16), sp(x2), 10
result : pc = 0x0000200A (target)
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
BLT is a conditional branch: when rs1 and rs2 satisfy the signed less than condition, the PC branches to the current PC plus the B-type offset; otherwise execution falls through.
The B-type branch offset is encoded in 2-byte units and reaches about +/-4 KiB from the current PC.
RISC-V conditional branches do not write rd and do not save a return address.
Official Spec Notes
These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.
No Link Register Write
Conditional branches only update the PC based on the comparison result. They do not write rd or save a return address; use JAL/JALR forms for calls and returns.
RISC-V Unprivileged ISA, RV32I control transfer instructionsCommon Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «blt x5, x6, loop # if x5 < x6 (signed), branch to loop».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is B-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Use BLTU for unsigned comparison
BGT/BLE synthesized by reversing BLT/BGE operands
FAQ
What is the BLT branch range?
Conditional branches use a B-type immediate, giving an approximate reach of +/-4 KiB from the current PC.
What is the difference between signed and unsigned branches?
BLT/BGE compare as signed integers; BLTU/BGEU compare as unsigned integers. BEQ/BNE only test equality of the bit patterns.