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BNE

RISC-V BNE Instruction Details

Instruction ManualB-type

Branch to PC-relative offset if rs1 is not equal to rs2

Instruction Syntax

bne rs1, rs2, offset
Operand Breakdown
Source rs1: first comparison operand.
Source rs2: second comparison operand.
Immediate offset: 13-bit signed branch offset (bit 0 is implicitly 0, ±4 KiB range).
RV32IRV64IControl TransferBranch
Related Search Terms
BNE instructionRISC-V BNEbne syntaxbne encodingbne B-typeBNE vs BEQbne branch

Instruction Behavior

BNE uses a 32-bit B-type encoding (opcode=1100011, funct3=001) and compares the XLEN-bit patterns of rs1 and rs2. Unequal values select current PC plus the sign-extended byte displacement; equal values select PC+4. The 12 encoded immediate bits plus implicit bit 0=0 form a signed 13-bit displacement, encoding even values from -4096 through 4094. With IALIGN=32, a taken target not aligned to four bytes raises an instruction-address-misaligned exception; this exception is impossible with IALIGN=16. General registers are unchanged.

BNE Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rs1
rs2
offset
bne
,
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

t2(x7)
0x00000007
s1(x9)
0x00000009
PC
0x00002000
31..25
24..20
19..15
14..12
11..7
6..0
0 000000
imm[12|10:5]
01001
rs2
00111
rs1
001
funct3
1000 0
imm[4:1|11]
1100011
opcode
Execution Data Path
instruction
0x00939863
opcode
1100011 -> BRANCH
funct3
001 -> BNE
rs1 / rs2 / pc
t2(x7)=0x00000007 / s1(x9)=0x00000009 / 0x00002000
B-imm
reassembled offset 16; bit 0 is implicit 0
condition
Not computed
PC
pc = 0x00002000; general registers unchanged
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00939863
syntax : bne x7, x9, 16
Pending result: Not computed
Current architectural state
pc = 0x00002000; general registers unchanged

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

BNE is a conditional branch: when rs1 and rs2 satisfy the not equal condition, the PC branches to the current PC plus the B-type offset; otherwise execution falls through.

B-type encodes 12 immediate-field bits; implicit bit 0=0 forms a signed 13-bit byte displacement. It encodes even values from -4096 through 4094; the target is the current PC plus the displacement.
RISC-V conditional branches do not write rd and do not save a return address.
An instruction-address-misaligned exception occurs only when the branch condition is true and its target violates IALIGN; a false condition does not raise that exception for an unaligned target.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120, §2.5.2

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Comparison & Detection

RV32I/RV64I example: PC=0x2000, a0=7, a1=9, target=0x2010 makes bne a0, a1, target select PC=0x2010; equality selects PC=0x2004.

Pre-Use Checklist

Syntax Check
  • Registers select x0 through x31 or their ABI aliases; B-type byte offsets must be even, from -4096 through 4094.
Semantic Check
  • BNE tests unequal XLEN-bit patterns, without a signed/unsigned distinction.
  • A taken branch targets the current PC plus offset; an untaken branch selects PC+4. General registers are unchanged. Only a taken target violating IALIGN raises instruction-address-misaligned.

Pitfalls / Common Confusions

The byte displacement must be even, from -4096 through 4094; a taken target must also be four-byte aligned with IALIGN=32.
Complementary to BEQ; ensure correct condition logic

FAQ

What is the BNE branch range?

The B-type byte displacement must be even and between -4096 and 4094. The target is the current branch PC plus the sign-extended displacement; a false condition selects PC+4.

What is the difference between signed and unsigned branches?

BLT/BGE compare as signed integers; BLTU/BGEU compare as unsigned integers. BEQ/BNE only test equality of the bit patterns.