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BLTU

RISC-V BLTU Instruction Details

Instruction ManualB-type

Branch if rs1 is less than rs2 (unsigned comparison)

Instruction Syntax

bltu rs1, rs2, offset
Operand Breakdown
Source rs1: first comparison operand.
Source rs2: second comparison operand.
Immediate offset: 13-bit signed branch offset (bit 0 is implicitly 0, ±4 KiB range).
RV32IControl TransferBranch
Related Search Terms
BLTU instructionRISC-V BLTUbltu syntaxbltu encodingbltu B-typeBLTU vs BLTbltu branch

Instruction Behavior

BLTU compares rs1 and rs2 as unsigned integers and branches if rs1 < rs2 (range ±4 KiB). A useful trick: signed array bounds checking can use a single BLTU, since any negative index (interpreted as a large unsigned value) will be greater than any nonnegative bound. BGTU can be synthesized by swapping operands.

BLTU Decode And Execute Animation

Uses the same rhythm as the ADDI page: machine-code fields, fixed-field identification, operand reads, instruction-specific execution, and ISA-visible state update.

rs1
rs2
offset
bltu
,
,
Execution Context
31..25
24..20
19..15
14..12
11..7
6..0
0 000000
imm[12|10:5]
01001
rs2
00100
rs1
110
funct3
0101 0
imm[4:1|11]
1100011
opcode
Execution Data Path
instruction
0x00926563
opcode
1100011 -> BRANCH
funct3
110 -> BLTU
rs1 / rs2 / pc
tp(x4)=0x00000004 / s1(x9)=0x00000009 / 0x00002000
B-imm
reassembled offset 10; bit 0 is implicit 0
condition
< -> taken
PC
pc = 0x0000200A (target)
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x00926563
syntax : bltu tp(x4), s1(x9), 10
result : pc = 0x0000200A (target)

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

BLTU is a conditional branch: when rs1 and rs2 satisfy the unsigned less than condition, the PC branches to the current PC plus the B-type offset; otherwise execution falls through.

The B-type branch offset is encoded in 2-byte units and reaches about +/-4 KiB from the current PC.
RISC-V conditional branches do not write rd and do not save a return address.
RISC-V Unprivileged ISA Manual: RV32I Base Integer Instruction Set

Official Spec Notes

These notes are checked against the RISC-V Unprivileged ISA manual and summarize operation semantics, immediate ranges, and edge behavior.

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «bltu x9, x10, error # if x9 < x10 (unsigned), branch to error».

Type Conversion

Understand this scenario with real code like «bltu x9, x10, error # if x9 < x10 (unsigned), branch to error».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is B-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Use BLT for signed comparison
Negative values become very large when interpreted as unsigned

FAQ

What is the BLTU branch range?

Conditional branches use a B-type immediate, giving an approximate reach of +/-4 KiB from the current PC.

What is the difference between signed and unsigned branches?

BLT/BGE compare as signed integers; BLTU/BGEU compare as unsigned integers. BEQ/BNE only test equality of the bit patterns.